From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x231.google.com (mail-wm0-x231.google.com [IPv6:2a00:1450:400c:c09::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DF830821D4 for ; Wed, 1 Mar 2017 06:42:33 -0800 (PST) Received: by mail-wm0-x231.google.com with SMTP id v186so111962063wmd.0 for ; Wed, 01 Mar 2017 06:42:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FJd9UMwucWND6VovMoT1bInxF5nsE/+q00L2o47dv+0=; b=Mi3cMYqYpr03Dlnm3L46sdlPauPdli0DZ1kMfUr+dcnznmdCFv6wfAs2h4XxBaPxIL eFTv3niWxftJMZ7gvOzTgIRliyl/KWaJbFOhAbEIJe2PUheqP5qW733DCNim5oiTxrx1 jwfrC8Fwm9XA+KjSjsa2MSK0GTYoa8h5alMvg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FJd9UMwucWND6VovMoT1bInxF5nsE/+q00L2o47dv+0=; b=YkcX5QRlBSCpnOVggY1MfdYFhTpIcMWd14KpveCAv4nq5k5q8CeEkJqfIelOIoHX45 aLllR8kM/HV0oFjkmOYDDjZVg9hFaBQGoUj+9JGEZjiOa3yL/K+xxUHm7KzaPfrop1nI 5Si7AOY8eXhq1gWjEsHza5Ib20RJt+rLy+lIkgf0ikG0Dvw305jnWlO6irhkQHtyEF+i RXRSKT887H087VSRsDy/dIQ2x/2Av+KhojyaTdGIPWedr/dyMnTgsgpsGxNesh60C55k uBzagFznRK2rgmFktntxNMmy9gkRXqDuy9Tvj0/R4w9v+j21zw4FNFP/ogD7RSrlJ5SW c1dw== X-Gm-Message-State: AMke39nTR2V4VpcBm2+Q8GPjKcbetd1zHomRndwrkQwbNXF1UBd0J1oiJGeV3AER0hNgiEhc X-Received: by 10.28.229.78 with SMTP id c75mr4036749wmh.20.1488379352455; Wed, 01 Mar 2017 06:42:32 -0800 (PST) Received: from localhost.localdomain ([105.147.1.203]) by smtp.gmail.com with ESMTPSA id h75sm6867958wrh.37.2017.03.01.06.42.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 01 Mar 2017 06:42:31 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, lersek@redhat.com Cc: Ard Biesheuvel Date: Wed, 1 Mar 2017 14:42:22 +0000 Message-Id: <1488379344-16273-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488379344-16273-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488379344-16273-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 2/4] ArmPkg/CpuDxe ARM: avoid unnecessary cache/TLB maintenance X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Mar 2017 14:42:34 -0000 Page and section entries in the page tables are updated using the helper ArmUpdateTranslationTableEntry(), which cleans the page table entry to the PoC, and invalidates the TLB entry covering the page described by the entry being updated. Since we may be updating section entries, we might be leaving stale TLB entries at this point (for all pages in the section except the first one), which will be invalidated wholesale at the end of SetMemoryAttributes(). At that point, all caches are cleaned *and* invalidated as well. This cache maintenance is costly and unnecessary. The TLB maintenance is only necessary if we updated any section entries, since any page by page entries that have been updated will have been invalidated individually by ArmUpdateTranslationTableEntry(). So drop the clean/invalidate of the caches, and only perform the full TLB flush if UpdateSectionEntries() was called. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c index 046620f79185..fe0ddee447b0 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -680,6 +680,7 @@ SetMemoryAttributes ( { EFI_STATUS Status; UINT64 ChunkLength; + BOOLEAN FlushTlbs; // // Ignore invocations that only modify permission bits @@ -688,6 +689,7 @@ SetMemoryAttributes ( return EFI_SUCCESS; } + FlushTlbs = FALSE; while (Length > 0) { if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) && Length >= TT_DESCRIPTOR_SECTION_SIZE) { @@ -700,6 +702,8 @@ SetMemoryAttributes ( Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes, VirtualMask); + + FlushTlbs = TRUE; } else { // @@ -728,16 +732,9 @@ SetMemoryAttributes ( Length -= ChunkLength; } - // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks - // flush and invalidate pages - //TODO: Do we really need to invalidate the caches everytime we change the memory attributes ? - ArmCleanInvalidateDataCache (); - - ArmInvalidateInstructionCache (); - - // Invalidate all TLB entries so changes are synced - ArmInvalidateTlb (); - + if (FlushTlbs) { + ArmInvalidateTlb (); + } return Status; } -- 2.7.4