From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22d.google.com (mail-wr0-x22d.google.com [IPv6:2a00:1450:400c:c0c::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C71A180318 for ; Mon, 6 Mar 2017 09:32:23 -0800 (PST) Received: by mail-wr0-x22d.google.com with SMTP id u108so121802025wrb.3 for ; Mon, 06 Mar 2017 09:32:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q7OImrWIYdjfIYo4orz1uf8yUoVXiJM1zpG5BraKCuA=; b=Tor9GAPZlXd/8LOy4vwE316zg3Qtqo7wq8gMlkWKrnbs8kqsJmXD5WgOCcXQ/zFnRs qgp61C1ubR96sGugGu10UGQrvony/1J+X+ziBVc+Xev62UbFYBQ+xtcThkGrLDMwHEF5 OW5Z/XITxsprLpC7wNH1XDeitZJkvrPgfh7i4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q7OImrWIYdjfIYo4orz1uf8yUoVXiJM1zpG5BraKCuA=; b=LEoLlgupmXkg4cZEHskLp3lDwqtzAfQgexJtYsSvV/SkTj/PuP/q5WJfcTVa3DNS1i DPgLUtX2umVlbXKCeGwVi6naDNbntTqISst57SsyvVwbL6Vn2ZViGMZunaCQuzrcvJm1 qQMVNXOEkQCnYvaOPj8v5oMI0OV3+cAeezKEAHI1ewU8q5Lt7+lqKbQzonVBcd8e3gQF kPoMAnjdlovdq5LzDp7B6zyZhdsTcBj3kGL0HyOaD2o7tSsym72pvjtmSMZMF5WF78IH DKUBhw5WHPi8vHdgcNSx//elO7UELMo/zVuhJRvl0Zg3iZLzXdUxyl9/uyylu3QNs218 X0Jg== X-Gm-Message-State: AMke39kmZpR8MWXMLsQsXca6vWeYOr/zFOdZ6mdX6bp9FOaGUc9v16LWQdLlrXeU7A09RW6Y X-Received: by 10.223.133.182 with SMTP id 51mr16394947wrt.39.1488821542173; Mon, 06 Mar 2017 09:32:22 -0800 (PST) Received: from ards-macbook-pro.c.hoisthospitality.com ([109.74.48.129]) by smtp.gmail.com with ESMTPSA id 136sm15704335wmg.12.2017.03.06.09.32.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 06 Mar 2017 09:32:21 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: lersek@redhat.com, Ard Biesheuvel Date: Mon, 6 Mar 2017 18:32:12 +0100 Message-Id: <1488821535-14795-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488821535-14795-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488821535-14795-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v3 1/4] ArmPkg/CpuDxe ARM: avoid splitting page table sections unnecessarily X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Mar 2017 17:32:24 -0000 Currently, any range passed to CpuArchProtocol::SetMemoryAttributes is fully broken down into page mappings if the start or the size of the region happens to be misaliged relative to the section size of 1 MB. This is going to result in memory being wasted on second level page tables when we enable strict memory permissions, given that we remap the entire RAM space non-executable (modulo the code bits) when the CpuArchProtocol is installed. So refactor the code to iterate over the range in a way that ensures that all naturally aligned section sized subregions are not broken up. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 51 +++++++++++++++++--- 1 file changed, 43 insertions(+), 8 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c index 89e429925ba9..16d6fcef9f1c 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -679,6 +679,11 @@ SetMemoryAttributes ( ) { EFI_STATUS Status; + UINT64 ChunkLength; + + if (Length == 0) { + return EFI_SUCCESS; + } // // Ignore invocations that only modify permission bits @@ -687,14 +692,44 @@ SetMemoryAttributes ( return EFI_SUCCESS; } - if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) { - // Is the base and length a multiple of 1 MB? - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes)); - Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask); - } else { - // Base and/or length is not a multiple of 1 MB - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes)); - Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask); + while (Length > 0) { + if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) && + Length >= TT_DESCRIPTOR_SECTION_SIZE) { + + ChunkLength = Length - Length % TT_DESCRIPTOR_SECTION_SIZE; + + DEBUG ((DEBUG_PAGE, + "SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n", + BaseAddress, ChunkLength, Attributes)); + + Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes, + VirtualMask); + } else { + + // + // Process page by page until the next section boundary, but only if + // we have more than a section's worth of area to deal with after that. + // + ChunkLength = TT_DESCRIPTOR_SECTION_SIZE - + (BaseAddress % TT_DESCRIPTOR_SECTION_SIZE); + if (ChunkLength + TT_DESCRIPTOR_SECTION_SIZE > Length) { + ChunkLength = Length; + } + + DEBUG ((DEBUG_PAGE, + "SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n", + BaseAddress, ChunkLength, Attributes)); + + Status = UpdatePageEntries (BaseAddress, ChunkLength, Attributes, + VirtualMask); + } + + if (EFI_ERROR (Status)) { + break; + } + + BaseAddress += ChunkLength; + Length -= ChunkLength; } // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks -- 2.7.4