From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22b.google.com (mail-wm0-x22b.google.com [IPv6:2a00:1450:400c:c09::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 457A78034A for ; Wed, 8 Mar 2017 03:51:50 -0800 (PST) Received: by mail-wm0-x22b.google.com with SMTP id 196so29635792wmm.1 for ; Wed, 08 Mar 2017 03:51:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=7tx6dYROa2ymw/thvSEQYRy44xWlM4uCJCeCIfVWFBo=; b=EonjTheUyHl3goi3RVQ6Ueo4ep1PE8+1B9KBGnyh7F7NZTQkSuuSGobqILmw/zSgSG JmeLxPTnxVjn0/Z8yLRblqSGG6nc9D1F9XuikRr8aMp/D8pEsC48KcWQkHNDHGgf6iHr yfTxhmUrbtDCAHR8DGA/oFhYGOjbmVC87Xo74= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=7tx6dYROa2ymw/thvSEQYRy44xWlM4uCJCeCIfVWFBo=; b=XHQQ4EU8e3uTcUKUvFR1ezDJyZ+rg1C+8UihvtKGCokotFmP0RUC+5368Lb797Mi/O WhQdKV3yXoITH5K6SLOdSWjnPAevdmF3VapiCtoU3VfONk6ghDRaShPr+wwIt78eGht5 iRs/olSXWWa8ab92D9jOeE7N6kKNcZR02Qsw1xf1oVyKMfUH3f18cU9HT0HIe/HzlRgj gAxQ9N+pBUPNi3aMIwk2D+Ab6Kqta5DEEEn1UsqBU9DEsDiacqelYk4yKwMoMKNXFdln Ym9gR3PY4vnhEldTK6dlxN/7w9E71V+DFlIPJT9GsGrRTOA4WWR0LiFb2rSCzSl6zbSH lgJg== X-Gm-Message-State: AMke39lZ4BNk4Vh9YMzIQJWwAE2fJxcVunSYmj/mMFK4uMoFicRK16g7R+kymIzrAq0CD0dP X-Received: by 10.28.154.7 with SMTP id c7mr5473327wme.119.1488973907782; Wed, 08 Mar 2017 03:51:47 -0800 (PST) Received: from ards-macbook-pro.c.hoisthospitality.com ([109.74.48.129]) by smtp.gmail.com with ESMTPSA id 189sm4395040wmm.31.2017.03.08.03.51.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Mar 2017 03:51:46 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, heyi.guo@Linaro.org Cc: Ard Biesheuvel Date: Wed, 8 Mar 2017 12:51:44 +0100 Message-Id: <1488973904-15031-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [PATCH] ArmPkg/CpuDxe: handle implied attributes in EfiAttributeToArmAttribute X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Mar 2017 11:51:50 -0000 Some memory attributes are implied by the memory type, e.g., device memory is always mapped non-executable and cached memory should have the inner shareable attribute. In order to prevent unnecessary memory attribute updates of mappings created early on, make EfiAttributeToArmAttribute() return these implied attributes in the same way as ArmMmuLib does already. This avoids false positives when looking for differences between current and desired mapping attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c index 7688846e70cb..3e216c7cb235 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -204,16 +204,20 @@ EfiAttributeToArmAttribute ( switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) { case EFI_MEMORY_UC: - ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY; + if (ArmReadCurrentEL () == AARCH64_EL2) { + ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK; + } else { + ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK; + } break; case EFI_MEMORY_WC: ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE; break; case EFI_MEMORY_WT: - ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH; + ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; break; case EFI_MEMORY_WB: - ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK; + ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; break; default: ArmAttributes = TT_ATTR_INDX_MASK; -- 2.7.4