From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot0-x242.google.com (mail-ot0-x242.google.com [IPv6:2607:f8b0:4003:c0f::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9CBF58036C for ; Tue, 21 Mar 2017 14:12:44 -0700 (PDT) Received: by mail-ot0-x242.google.com with SMTP id i1so23770653ota.3 for ; Tue, 21 Mar 2017 14:12:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:subject:to:cc:date:message-id:user-agent:mime-version :content-transfer-encoding; bh=YO2epWwThxP9e+puTvLJFSP3vUPVjSDNm1chABEnIcA=; b=lolEeB18UIoC4Gnkw1ApAWBhZpZRrFOZyhxQaj8nd3iMuKIKvzETN5cQNzTNSnoMM0 7JbPTOUWywa1NSApw2OF3pfxdc98iXQd2ETkQb01XVtYCUCtPyyK2HwsLXoSbvA5Nank IJ2B40X2BwZsW6oFIW7+6hoBYB0QUP4ntY08v2rxj8fuUoyYmQMUXy7yhOsY3BgJ/GRJ JYT/scFdfX2VR2cL/TDOvin4hpG5qAhSu30QO8hHbWkbSSyLnWj9rRPbPSUhZa32Rwsn f7VbuqxH9OG2Sb7YxFggXivfYmt55ZUll8iVFAn8x5pfZ2irQqhYHSg76EJv7Xjq86cx XoKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:date:message-id:user-agent :mime-version:content-transfer-encoding; bh=YO2epWwThxP9e+puTvLJFSP3vUPVjSDNm1chABEnIcA=; b=fDdgre1Yqijla8g56XT0DZt1/VLS+nzj9VAETaWXfOPcqIEp0ZxL5qhMya+yLj3EpI r3CRkkuXT+5UFIoQwov+K/AgoC8p1XDKkI6AkPThWDoJc4VwbnsQep87LgwF83hTQjrc acXL2ufpJTmaoLuaff+f3dYIx3rSy6CACWsDDaQolNUxgCrTWVzTkkw+xZM+n6qLZcHC SRw9y4fM4V3s8EU+RYIghxryzAfJlFylplhp/0aj2I11WUx/IbbrJMyPvII8Ve5tiR5h f9z/CBxynhBJnRE88LBTOY0CpuYS8PAiCoE74HRST6hiKqER6B4mLt6SPbWpe+ol5lPk PdmQ== X-Gm-Message-State: AFeK/H3tHZ0ZfRo47AUYkAw3lXg0ZhE76zMbJpTEzpZ120Az89IWi9m8WQ0zxEWmr1I9og== X-Received: by 10.157.24.45 with SMTP id b42mr18520718ote.212.1490130763859; Tue, 21 Mar 2017 14:12:43 -0700 (PDT) Received: from [127.0.1.1] ([165.204.77.1]) by smtp.gmail.com with ESMTPSA id d38sm9348417otc.5.2017.03.21.14.12.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Mar 2017 14:12:42 -0700 (PDT) From: Brijesh Singh X-Google-Original-From: Brijesh Singh To: michael.d.kinney@intel.com, jordan.l.justen@intel.com, edk2-devel@ml01.01.org, lersek@redhat.com, liming.gao@intel.com Cc: leo.duran@amd.com, brijesh.singh@amd.com, Thomas.Lendacky@amd.com Date: Tue, 21 Mar 2017 17:12:41 -0400 Message-ID: <149013076154.27235.10725020825643505862.stgit@brijesh-build-machine> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Subject: [RESEND] [RFC PATCH v2 00/10] x86: Secure Encrypted Virtualization (AMD) X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Mar 2017 21:12:44 -0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit (Sorry for churn, correcting Laszlo's email address) This RFC series provides support for AMD's new Secure Encrypted Virtualization (SEV) feature. SEV is an extension to the AMD-V architecture which supports running multiple VMs under the control of a hypervisor. The SEV feature allows the memory contents of a virtual machine (VM) to be transparently encrypted with a key unique to the guest VM. The memory controller contains a high performance encryption engine which can be programmed with multiple keys for use by a different VMs in the system. The programming and management of these keys is handled by the AMD Secure Processor firmware which exposes a commands for these tasks. SEV guest VMs have the concept of private and shared memory. Private memory is encrypted with the guest-specific key, while shared memory may be encrypted with hypervisor key. Certain types of memory (namely instruction pages and guest page tables) are always treated as private memory by the hardware. For data memory, SEV guest VMs can choose which pages they would like to be private. The choice is done using the standard CPU page tables using the C-bit, and is fully controlled by the guest. Due to security reasons all the DMA operations inside the guest must be performed on shared pages (C-bit clear). Note that since C-bit is only controllable by the guest OS when it is operating in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware forces the C-bit to a 1. The following links provide additional details: AMD Memory Encryption whitepaper: http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_Memory_Encryption_Whitepaper_v7-Public.pdf AMD64 Architecture Programmer's Manual: http://support.amd.com/TechDocs/24593.pdf SME is section 7.10 SEV is section 15.34 Secure Encrypted Virutualization Key Management: http://support.amd.com/TechDocs/55766_SEV-KM API_Specification.pdf KVM Forum Presentation: http://www.linux-kvm.org/images/7/74/02x08A-Thomas_Lendacky-AMDs_Virtualizatoin_Memory_Encryption_Technology.pdf [1] http://marc.info/?l=linux-mm&m=148846752931115&w=2 --- Patch series is based on commit 5d5a190 (ArmVirtPkg/HighMemDxe: check new regions against GCD memory space map) plus I have cherry-picked https://lists.01.org/pipermail/edk2-devel/2017-March/008109.html and https://lists.01.org/pipermail/edk2-devel/2017-March/008756.html. source is also available @ https://github.com/codomania/edk2/tree/sev-rfc-2 The patch series is tested with OvmfIa32.dsc, OvmfIa32X64.dsc and OvmfX64.dsc. Since memory encryption bit is not accessiable when processor is in 32-bit mode hence any DMA access in this mode would cause assert. I have also tested the suspend and resume path, it seems to be working fine. I still need to work to finish adding the SEV Dma support in QemuFwCfgS3Lib package (see TODO). Changes since v1: - bug fixes in OvmfPkg/ResetVector (pointed by Tom Lendacky) - add SEV CPUID and MSR register definition in standard include file - remove the MemEncryptLib dependency from PlatformPei. Move AmdSevInitialize() implementation in local file inside the PlatformPei package - rename MemCryptSevLib to MemEncryptSevLib and add functions to set or clear memory encryption attribute on memory region - integerate SEV support in BmDmaLib - split QemuFwCfgDxePei.c into QemuFwCfgDxe.c and QemuFwCfgPei.c to allow building seperate QemuFwCfgLib for Dxe and Pei phase (recommended by Laszlo Ersek) - add SEV support in QemuFwCfgLib - clear the memory encryption attribute from framebuffer memory region TODO: - add support for accessing QEMU system flash device when SEV is enabled - add support for DMA operation in QemuFwCfgS3Lib when SEV is enabled - investigate SMM/SMI support - add virtio support Brijesh Singh (10): OvmfPkg/Include: Define SEV specific CPUID and MSR OvmfPkg/ResetVector: add memory encryption mask when SEV is enabled OvmfPkg/PlatformPei: Add Secure Encrypted Virutualization (SEV) support OvmfPkg/BaseMemcryptSevLib: Add SEV helper library OvmfPkg/DxeBmDmaLib: Import DxeBmDmaLib package OvmfPkg/DxeBmDmaLib: Fix AllocateBounceBuffer parameter OvmfPkg/BmDmaLib: Add SEV support OvmfPkg/QemuFwCfgLib: Provide Pei and Dxe specific library support OvmfPkg/QemuFwCfgLib: Add Secure Encrypted Virtualization (SEV) support OvmfPkg/QemuVideoDxe: Clear the C-bit from framebuffer region when SEV is enabled OvmfPkg/Include/Library/BmDmaLib.h | 0 OvmfPkg/Include/Library/MemEncryptSevLib.h | 69 +++ OvmfPkg/Include/Register/AmdSevMap.h | 133 +++++++ .../BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf | 46 ++ .../BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c | 124 ++++++ .../BaseMemEncryptSevLib/X64/MemEncryptSevLib.c | 120 ++++++ .../BaseMemEncryptSevLib/X64/VirtualMemory.c | 304 +++++++++++++++ .../BaseMemEncryptSevLib/X64/VirtualMemory.h | 158 ++++++++ OvmfPkg/Library/DxeBmDmaLib/DxeBmDmaLib.c | 409 ++++++++++++++++++++ OvmfPkg/Library/DxeBmDmaLib/DxeBmDmaLib.inf | 42 ++ OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c | 189 +++++++++ OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf | 8 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c | 112 +++++ .../Library/QemuFwCfgLib/QemuFwCfgLibInternal.h | 38 ++ OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c | 209 ++++++++++ OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiDxe.c | 116 ------ OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf | 8 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c | 82 ++++ OvmfPkg/OvmfPkgIa32.dsc | 10 OvmfPkg/OvmfPkgIa32X64.dsc | 10 OvmfPkg/OvmfPkgX64.dsc | 10 OvmfPkg/PlatformPei/AmdSev.c | 97 +++++ OvmfPkg/PlatformPei/Platform.c | 1 OvmfPkg/PlatformPei/Platform.h | 5 OvmfPkg/PlatformPei/PlatformPei.inf | 2 OvmfPkg/QemuVideoDxe/Gop.c | 15 + OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf | 1 OvmfPkg/ResetVector/Ia32/PageTables64.asm | 62 +++ 28 files changed, 2252 insertions(+), 128 deletions(-) copy MdeModulePkg/Include/Library/BmDmaLib.h => OvmfPkg/Include/Library/BmDmaLib.h (100%) create mode 100644 OvmfPkg/Include/Library/MemEncryptSevLib.h create mode 100644 OvmfPkg/Include/Register/AmdSevMap.h create mode 100644 OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevLib.inf create mode 100644 OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c create mode 100644 OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c create mode 100644 OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.c create mode 100644 OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h create mode 100644 OvmfPkg/Library/DxeBmDmaLib/DxeBmDmaLib.c create mode 100644 OvmfPkg/Library/DxeBmDmaLib/DxeBmDmaLib.inf create mode 100644 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c copy OvmfPkg/Library/QemuFwCfgLib/{QemuFwCfgLib.inf => QemuFwCfgDxeLib.inf} (82%) create mode 100644 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c delete mode 100644 OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiDxe.c rename OvmfPkg/Library/QemuFwCfgLib/{QemuFwCfgLib.inf => QemuFwCfgPeiLib.inf} (83%) create mode 100644 OvmfPkg/PlatformPei/AmdSev.c -- Brijesh Singh