From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot0-x243.google.com (mail-ot0-x243.google.com [IPv6:2607:f8b0:4003:c0f::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9D47E8036C for ; Tue, 21 Mar 2017 14:12:50 -0700 (PDT) Received: by mail-ot0-x243.google.com with SMTP id i1so23771064ota.3 for ; Tue, 21 Mar 2017 14:12:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:subject:to:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=z00WS5PDtCeLzzF533HQhxajYoAQQq+6GklawBjRjaI=; b=Lrhrb3NZu7/jgNhafM9mYEYIrur7LT4Ttid4qrypCWj3m4cgdnor5Mou9YihXPH0tZ YhMggAwmzjY+vyGKz75I1FkAGCWZhiLNV7KUG4pcY1sH3nQvj2BzlDGqyDCiJT1EOdcE g9SUN3IHJhKNQDSHco8Ofo1OV8JTA+n66zQ6hGBv8ot7SWWCrN/RHwLqdrcVKraYVDZY UMHGDauIhF5lJuV2B92q9So0UCGBYa6zD/JHvhyPsLO5PRrVuL9W2rraaMUD+2vBLQFW pm3mLQqCOGk+gdpNGy92kWuXVBUDV2OhSWWfsVanTmaU2x3LCwoVlwvwTqYrxt/zntFS Xv3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=z00WS5PDtCeLzzF533HQhxajYoAQQq+6GklawBjRjaI=; b=mCaF55G/74DatNJpZdZ8MFciq9F3u8LE1maaehs+9TkeH51wnBnGFf6al84Ao/Gwj0 7wToV6xDfbtUdxtYvpu1R88Ya/HClSpIL77MnkZelSzofQR5VDtJNyYmy9/t58cNWxkQ gXqT6/5gC+t9KrAlFSW6VJM+pfFymRtpGt8lga1AhkXa8LRgb0vhF9MkJ4hOVRlvG3Er 30y5Gr03IQ/uj2DAdD3DFvIkWp91mNUopW3ocrU1dcqlVPDQmme0RB6tgeEV+MMMp6sI P02IIqicdu12DDZR6GSFQhyNwh89PfTjnWLydsoH39WL204tCQJ/8D3wr12D9N+dpogM ILFw== X-Gm-Message-State: AFeK/H0GKZgLd1LuGWtf55+4stUBS4ICaGSvsnG58biJ7CG9qgtNYVVmSQvzvtAI+BpBzA== X-Received: by 10.157.17.52 with SMTP id g49mr23630487ote.222.1490130769954; Tue, 21 Mar 2017 14:12:49 -0700 (PDT) Received: from [127.0.1.1] ([165.204.77.1]) by smtp.gmail.com with ESMTPSA id t64sm9222331otb.2.2017.03.21.14.12.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Mar 2017 14:12:49 -0700 (PDT) From: Brijesh Singh X-Google-Original-From: Brijesh Singh To: michael.d.kinney@intel.com, jordan.l.justen@intel.com, edk2-devel@ml01.01.org, lersek@redhat.com, liming.gao@intel.com Cc: leo.duran@amd.com, brijesh.singh@amd.com, Thomas.Lendacky@amd.com Date: Tue, 21 Mar 2017 17:12:49 -0400 Message-ID: <149013076888.27235.3173588515291478806.stgit@brijesh-build-machine> In-Reply-To: <149013076154.27235.10725020825643505862.stgit@brijesh-build-machine> References: <149013076154.27235.10725020825643505862.stgit@brijesh-build-machine> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Subject: [RFC PATCH v2 01/10] OvmfPkg/Include: Define SEV specific CPUID and MSR X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Mar 2017 21:12:50 -0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit The patch defines AMD's Memory Encryption Information CPUID leaf (0x8000_001F). The complete description for this CPUID leaf is available in APM volume 2 [1] Section 15.34 (Secure Encrypted Virtualization). [1] http://support.amd.com/TechDocs/24593.pdf Signed-off-by: Brijesh Singh --- OvmfPkg/Include/Register/AmdSevMap.h | 133 ++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 OvmfPkg/Include/Register/AmdSevMap.h diff --git a/OvmfPkg/Include/Register/AmdSevMap.h b/OvmfPkg/Include/Register/AmdSevMap.h new file mode 100644 index 0000000..de80f39 --- /dev/null +++ b/OvmfPkg/Include/Register/AmdSevMap.h @@ -0,0 +1,133 @@ +/** @file + +AMD Secure Encrypted Virtualization (SEV) specific CPUID and MSR definitions + +The complete description for this CPUID leaf is available in APM volume 2 (Section 15.34) +http://support.amd.com/TechDocs/24593.pdf + +Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
+ +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __AMD_SEV_MAP_H__ +#define __AMD_SEV_MAP_H__ + +#pragma pack (1) + +#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F + +/** + CPUID Memory Encryption support information EAX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Secure Memory Encryption (Sme) Support + /// + UINT32 SmeBit:1; + + /// + /// [Bit 1] Secure Encrypted Virtualization (Sev) Support + /// + UINT32 SevBit:1; + + /// + /// [Bit 2] Page flush MSR support + /// + UINT32 PageFlushMsrBit:1; + + /// + /// [Bit 3] Encrypted state support + /// + UINT32 SevEsBit:1; + + /// + /// [Bit 4:31] Reserved + /// + UINT32 ReservedBits:28; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EAX; + +/** + CPUID Memory Encryption support information EBX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0:5] Page table bit number used to enable memory encryption + /// + UINT32 PtePosBits:6; + + /// + /// [Bit 6:11] Reduction of system physical address space bits when memory encryption is enabled + /// + UINT32 ReducedPhysBits:5; + + /// + /// [Bit 12:31] Reserved + /// + UINT32 ReservedBits:21; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EBX; + +/** + Secure Encrypted Virtualization (SEV) status register + +**/ +#define MSR_SEV_STATUS 0xc0010131 + +/** + MSR information returned for #MSR_SEV_STATUS +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled + /// + UINT32 SevBit:1; + + /// + /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled + /// + UINT32 SevEsBit:1; + + UINT32 Reserved:30; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SEV_STATUS_REGISTER; + +#endif