From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22e.google.com (mail-wr0-x22e.google.com [IPv6:2a00:1450:400c:c0c::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CC5CD20080934 for ; Wed, 5 Apr 2017 13:38:47 -0700 (PDT) Received: by mail-wr0-x22e.google.com with SMTP id o21so4442726wrb.2 for ; Wed, 05 Apr 2017 13:38:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=34EHLjezh01HAgfUa0Z/zt0CjFglqzpsRDqmyNqobfE=; b=NC1gO2Cg4RTgfzhJvws+pP8JAOgjCLJeBzg7Vkh7yIe/VR8a8kRgVqZoPOmE6/32YK fjDrbEnTOUeiRmJ+91Evbu1tV4BpU1+Z5e6rLE30PDDvF2KLX6eKY1QK10N/HGEG3Ep2 fxA8jblsS81+kIUDMI384eSjyv7Ft3zonUKbU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=34EHLjezh01HAgfUa0Z/zt0CjFglqzpsRDqmyNqobfE=; b=DBFstH+r0r25rpVofzLONBXgQcveV6FSuZJv0jVoZmiONOQ4q+Fr3ZDgxiETmvFuhc 5Tr3KX8GtG+OC8nUVVh2AYLhkry8u4w0Xlp6GglXC2RHQIH6at3ytb0yV1sCI5CvQ0V8 nzDGp46+jePdS+LJe+0qr1Vo7jd0cWuY2ncsqa/udEOaXEqEve7zvo4X5g/d/deCIrLb RdlNxdrwqYYJd/zrWariuXuZLvBwPTZ4Vczd+48SdxcLVCWv+XYVrp8RoObzaJ8bJPR7 ao4f5qxzDAZwXkKc5AqsIz5HkPjIsi6MlwPQm9coXpcMb4vOUfS9mIbeKHWtqJn0Xg+G neYg== X-Gm-Message-State: AFeK/H0EFGwGdR+K5cpQ/licaXvYB7BvIytGQqwyW17cQQWMiElWrybJhUPytEAlv88Q8mTh X-Received: by 10.28.33.66 with SMTP id h63mr21476840wmh.86.1491424725764; Wed, 05 Apr 2017 13:38:45 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id b199sm23690032wmb.13.2017.04.05.13.38.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 05 Apr 2017 13:38:44 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, jeremy.linton@arm.com Cc: Ard Biesheuvel Date: Wed, 5 Apr 2017 21:38:32 +0100 Message-Id: <1491424713-5203-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [PATCH 1/2] ArmPlatformPkg/HdLcdArmVExpressLib: use write-combine mapping for VRAM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Apr 2017 20:38:48 -0000 Replace the uncached memory mapping of the framebuffer with a write- combining one. This improves performance, and avoids issues with unaligned accesses and DC ZVA instructions performed by the accelerated memcpy/memset routines. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c index a57846715ed7..d6d47545c824 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c @@ -143,7 +143,7 @@ LcdPlatformGetVram ( ASSERT_EFI_ERROR(Status); // Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable. - Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); + Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_WC); ASSERT_EFI_ERROR(Status); if (EFI_ERROR(Status)) { gBS->FreePool (VramBaseAddress); -- 2.7.4