From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x235.google.com (mail-wr0-x235.google.com [IPv6:2a00:1450:400c:c0c::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 74188203BF030 for ; Wed, 5 Apr 2017 13:38:49 -0700 (PDT) Received: by mail-wr0-x235.google.com with SMTP id w43so30665048wrb.0 for ; Wed, 05 Apr 2017 13:38:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lfoKuHMVyW5qfNXR9WVPzH6IjhKaSqvA1j4YA2kTeFg=; b=T2z9qlnQcQy0Nli++pNhrWL+WAiukg/R+jM+XspuqtVf0CTv2vNIeDMvAHZNZN/q34 j4uKM0zmkRJGEpLk4GJcO5LH5CK7NJorB4RzrfNytTG/aVMFSVMtABA9LR7Wv+Jti0uP H4L8gzrU7TsxM5BEmozcXE5YYN+9bASFa0F3M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lfoKuHMVyW5qfNXR9WVPzH6IjhKaSqvA1j4YA2kTeFg=; b=ZHeJoCYuVfXrWEbLOFcyZqdTu/qeThG7AKxFeeATnBTT8a2hrHIIXZ7YMEoXDxGk9T U51oGh5q+gx5Oy3o1fCIDZ5tQuJ2z8YzeGro8b0tIb0WeCmAa3c4ire3ZuC0pM4KLigc ++UhXMl0Hc1Tgz/pClvl7l1kBJtd2lFFJ4hEfbAKMUok7+UVQYYBoSDyzW0qjuuIxDPF CUuqbygAB8i2kpciMeTXiZJUDUhr54MEV+K260OIa3aRsSRAaZCThxV56h9NWCYtx7HC LkwUuzN7+XGwlhgZRCx/IqAIPxBOlIYmnZW/99NPqaaC7DFnoqGE5Lk4wmsoZZUXKw6w RwUg== X-Gm-Message-State: AFeK/H24OQ5pRVPRII7G7iWwSPTE+yFNAhfnfb43vhAZAEWkYVdQmV5lqB14tdimlCmtYk3S X-Received: by 10.28.140.19 with SMTP id o19mr21432530wmd.123.1491424727555; Wed, 05 Apr 2017 13:38:47 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id b199sm23690032wmb.13.2017.04.05.13.38.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 05 Apr 2017 13:38:46 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, jeremy.linton@arm.com Cc: Ard Biesheuvel Date: Wed, 5 Apr 2017 21:38:33 +0100 Message-Id: <1491424713-5203-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491424713-5203-1-git-send-email-ard.biesheuvel@linaro.org> References: <1491424713-5203-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 2/2] ArmPlatformPkg/PL111LcdArmVExpressLib: use write-combine mapping for VRAM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Apr 2017 20:38:49 -0000 Replace the uncached memory mapping of the framebuffer with a write- combining one. This improves performance, and avoids issues with unaligned accesses and DC ZVA instructions performed by the accelerated memcpy/memset routines. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c index 2000c9bdf436..d18d6b3e1665 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c @@ -192,7 +192,7 @@ LcdPlatformGetVram ( ASSERT_EFI_ERROR(Status); // Mark the VRAM as un-cachable. The VRAM is inside the DRAM, which is cachable. - Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); + Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_WC); ASSERT_EFI_ERROR(Status); if (EFI_ERROR(Status)) { gBS->FreePool(VramBaseAddress); -- 2.7.4