From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-x241.google.com (mail-oi0-x241.google.com [IPv6:2607:f8b0:4003:c06::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 54FF421951C84 for ; Tue, 25 Apr 2017 09:36:20 -0700 (PDT) Received: by mail-oi0-x241.google.com with SMTP id w12so7958660oiw.0 for ; Tue, 25 Apr 2017 09:36:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nIFJOt/eHHKKCgx/s9SD1ncW9c8NR53pGMzJXXoVg84=; b=WSbg/TFriEcgSArlwMZWqA4HY8n3Ro+RuF8Btm1yLDbwF9BbM8tF4uyfncTjEuHksg 98JKXQO/Kgk8tNnsxW7vLlOrxzECEixx7zosiqdcAftANY0y3mxnrC0wpZfXZFBuJuC6 XeR9yQurgS1ofn8RTgsHT7RB7tpAs5kSLn2Z4789DL9qmGTo9xzArdk3DM3XEP9gfnya RcXKX8pTnte8AupqllgfXROuB8xgdUtUatNq1XhtkQXeuUa4beNbo9Jf3Nw0o2N4jhQG b6IAOy7+j+5vdaxgKUEqG3JPBe/VlpITWT1qJkAP0kJCWKelsv4Fo42yJxBHefFc1FrH Gyjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nIFJOt/eHHKKCgx/s9SD1ncW9c8NR53pGMzJXXoVg84=; b=E+pFr+gP85XiACn1XaEPMLphhIMiGMpcDDu9EweoU0iQd0AjptIsqPWAIuBjlfZpjp T7LUsKc/z/MulLD9dtw/k4roEuIoo6ORuQ877x4+ei1sY68P28/9T+UkE+8O9r366Q1n dqaXua0V5u94nzDfX/E5tb82pt5qK3qCHaOqzYCI+Yq8RVER/bZA4LKQnXO/yL1TR7UX POoQ/So44pbx0/ehnQRF07xwwgKj2a+9dCQxFiDnsUEj4ORtckImfk5/OQn/JUQ4mjWK m3nsaO2dO/VQ7GXejfdRQVacWDDQdvOy2CWsqaEMz/tcTpw/rgeMjIrxl3z37N8WDmPt JtQw== X-Gm-Message-State: AN3rC/6pMYwjOz9be2OQDXXtE5WXqxMJ+73bGSLjO7Jmd0XGCo7l8qv9 M0m7i3Gzbr9Rgvh+5Gw= X-Received: by 10.202.196.70 with SMTP id u67mr17828245oif.190.1493138179512; Tue, 25 Apr 2017 09:36:19 -0700 (PDT) Received: from brijesh-build-machine.amd.com ([165.204.77.1]) by smtp.gmail.com with ESMTPSA id j17sm9666356ota.24.2017.04.25.09.36.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 25 Apr 2017 09:36:19 -0700 (PDT) From: Brijesh Singh To: edk2-devel@lists.01.org, lersek@redhat.com, jordan.l.justen@intel.com Cc: jiewen.yao@intel.com, leo.duran@amd.com, star.zeng@intel.com, liming.gao@intel.com, ard.biesheuvel@linaro.org, brijesh.singh@amd.com, William.Tambe@amd.com, thomas.lendacky@amd.com Date: Tue, 25 Apr 2017 12:34:19 -0400 Message-Id: <1493138064-7816-11-git-send-email-brijesh.ksingh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493138064-7816-1-git-send-email-brijesh.ksingh@gmail.com> References: <1493138064-7816-1-git-send-email-brijesh.ksingh@gmail.com> Subject: [RFC v3 10/15] OvmfPkg/QemuFwCfgLib: Implement SEV internal function for SEC phase X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Apr 2017 16:36:20 -0000 From: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh --- OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf | 1 + OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c | 57 ++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf index 7a96575d1851..b782ac6c0aa2 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf @@ -45,4 +45,5 @@ [LibraryClasses] DebugLib IoLib MemoryAllocationLib + MemEncryptSevLib diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c index 465ccbe90dad..cd04cc814063 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c @@ -6,6 +6,7 @@ Copyright (C) 2013, Red Hat, Inc. Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this @@ -18,6 +19,7 @@ #include #include +#include #include "QemuFwCfgLibInternal.h" @@ -94,3 +96,58 @@ InternalQemuFwCfgDmaIsAvailable ( { return FALSE; } + +/** + + Returns a boolean indicating whether SEV is enabled + + @retval TRUE SEV is enabled + @retval FALSE SEV is disabled +**/ +BOOLEAN +InternalQemuFwCfgSevIsEnabled ( + VOID + ) +{ + return MemEncryptSevIsEnabled (); +} + +/** + Allocate a bounce buffer for SEV DMA. + + @param[in] NumPage Number of pages. + @param[out] Buffer Allocated DMA Buffer pointer + +**/ +VOID +InternalQemuFwCfgSevDmaAllocateBuffer ( + IN UINT32 NumPages, + OUT VOID **Buffer + ) +{ + // + // We should never reach here + // + ASSERT (FALSE); + CpuDeadLoop (); +} + +/** + Free the DMA buffer allocated using InternalQemuFwCfgSevDmaAllocateBuffer + + @param[in] NumPage Number of pages. + @param[in] Buffer DMA Buffer pointer + +**/ +VOID +InternalQemuFwCfgSevDmaFreeBuffer ( + IN VOID *Buffer, + IN UINT32 NumPages + ) +{ + // + // We should never reach here + // + ASSERT (FALSE); + CpuDeadLoop (); +} -- 2.7.4