From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-x241.google.com (mail-oi0-x241.google.com [IPv6:2607:f8b0:4003:c06::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9DB2A21951C89 for ; Tue, 25 Apr 2017 09:36:21 -0700 (PDT) Received: by mail-oi0-x241.google.com with SMTP id m34so28208661oik.2 for ; Tue, 25 Apr 2017 09:36:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8yYLzRDrLmYdjlwRRXyxzq0PCt6MGq4XhnPE+jKZslY=; b=vXp85ZhTUEjpC5qSzghG2/gnXbRMGUC2mxeFS40tx85JUsmF4yuqzfE9hVL3ep60Cd hOcu74r9bQGYLh/1UHR77ZT22Y7FkLLZgNsnQACo8eI0JbgoN1zFRJLp4hkoJyqaJHWS IRKPkcn9IVS+zD8iLncZL83hSGLcvYOGPhfFFwI+NqOqS66Eyy3kbVnUIvqrYrmKnNX9 gc33K9H4CEifSYETH1v6KO58RdmC2uRq1v98sadrR2c4PyKUUQQPQfcN6UyFEpFKgdDw 1Fhjm+PQORPSETDurvGa1+ETkpi+q3PSLSSoGVHx7y32cC7/P4mlTVb257pmeuFpaptd N2ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8yYLzRDrLmYdjlwRRXyxzq0PCt6MGq4XhnPE+jKZslY=; b=RD+ZKAlueBRqORM2UF8f/ehsO+cLNOXJ9beOix6v9r/VDsYYBruuGQcMLncDCU9TEg 6ap9HjoitrGqoyeGdVhq4uq1yzkuYGAkhCF6JazDJs11utsbp7IfH/DshbY46R6UL6k+ m/je5n+Z3YUiZJD+ii2e8Gq4kgz1rVZncYC8jeb8SrT5XKQ7GXya0ClQEmqNvt2A/uXf ZmlpB3/z2ZPRICrGS8UqGw2J9VtYYHhZchFJ4YhteLQd1U17yky19ZGcpRi2Xp5bxA1U ItmVgZKv+EJ8Gls2QPTnvyp1NcEkxX+pexYTYnMKiY/Zb9h6sbwdWKq/7mCsGWFE3Fla 9z2Q== X-Gm-Message-State: AN3rC/4DULuIWtjrDZNuIEN9q7QUSgJ/TfS4UUX1hvf4zn0T+GcPkvqj qWjuWTCQhW/a/g== X-Received: by 10.157.54.2 with SMTP id w2mr18187297otb.104.1493138180956; Tue, 25 Apr 2017 09:36:20 -0700 (PDT) Received: from brijesh-build-machine.amd.com ([165.204.77.1]) by smtp.gmail.com with ESMTPSA id j17sm9666356ota.24.2017.04.25.09.36.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 25 Apr 2017 09:36:20 -0700 (PDT) From: Brijesh Singh To: edk2-devel@lists.01.org, lersek@redhat.com, jordan.l.justen@intel.com Cc: jiewen.yao@intel.com, leo.duran@amd.com, star.zeng@intel.com, liming.gao@intel.com, ard.biesheuvel@linaro.org, brijesh.singh@amd.com, William.Tambe@amd.com, thomas.lendacky@amd.com Date: Tue, 25 Apr 2017 12:34:20 -0400 Message-Id: <1493138064-7816-12-git-send-email-brijesh.ksingh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493138064-7816-1-git-send-email-brijesh.ksingh@gmail.com> References: <1493138064-7816-1-git-send-email-brijesh.ksingh@gmail.com> Subject: [RFC v3 11/15] OvmfPkg/QemuFwCfgLib: Implement SEV internal functions for PEI phase X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Apr 2017 16:36:21 -0000 From: Brijesh Singh The patch implements the SEV specific internal fucntion for PEI phase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh --- OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf | 1 + OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c | 72 +++++++++++++++++++- 2 files changed, 71 insertions(+), 2 deletions(-) diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf index 4f966a85088a..b97b475c7cad 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf @@ -47,4 +47,5 @@ [LibraryClasses] DebugLib IoLib MemoryAllocationLib + MemEncryptSevLib diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c index ac05f4c347f3..1696512bccaf 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c @@ -4,6 +4,7 @@ Copyright (C) 2013, Red Hat, Inc. Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this @@ -14,8 +15,10 @@ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/ +#include #include #include +#include #include "QemuFwCfgLibInternal.h" @@ -76,8 +79,18 @@ QemuFwCfgInitialize ( if ((Revision & FW_CFG_F_DMA) == 0) { DEBUG ((DEBUG_INFO, "QemuFwCfg interface (IO Port) is supported.\n")); } else { - mQemuFwCfgDmaSupported = TRUE; - DEBUG ((DEBUG_INFO, "QemuFwCfg interface (DMA) is supported.\n")); + // + // If SEV is enabled then we do not support DMA operations in PEI phase. + // This is mainly because DMA in SEV guest requires using bounce buffer + // (which need to allocate dynamic memory and allocating a PAGE size'd + // buffer can be challenge in PEI phase) + // + if (InternalQemuFwCfgSevIsEnabled ()) { + DEBUG ((DEBUG_INFO, "SEV: QemuFwCfg fallback to IO Port interface.\n")); + } else { + mQemuFwCfgDmaSupported = TRUE; + DEBUG ((DEBUG_INFO, "QemuFwCfg interface (DMA) is supported.\n")); + } } return RETURN_SUCCESS; } @@ -114,3 +127,58 @@ InternalQemuFwCfgDmaIsAvailable ( { return mQemuFwCfgDmaSupported; } + +/** + + Returns a boolean indicating whether SEV is enabled + + @retval TRUE SEV is enabled + @retval FALSE SEV is disabled +**/ +BOOLEAN +InternalQemuFwCfgSevIsEnabled ( + VOID + ) +{ + return MemEncryptSevIsEnabled (); +} + +/** + Allocate a bounce buffer for SEV DMA. + + @param[in] NumPage Number of pages. + @param[out] Buffer Allocated DMA Buffer pointer + +**/ +VOID +InternalQemuFwCfgSevDmaAllocateBuffer ( + IN UINT32 NumPages, + OUT VOID **Buffer + ) +{ + // + // We should never reach here + // + ASSERT (FALSE); + CpuDeadLoop (); +} + +/** + Free the DMA buffer allocated using InternalQemuFwCfgSevDmaAllocateBuffer + + @param[in] NumPage Number of pages. + @param[in] Buffer DMA Buffer pointer + +**/ +VOID +InternalQemuFwCfgSevDmaFreeBuffer ( + IN VOID *Buffer, + IN UINT32 NumPages + ) +{ + // + // We should never reach here + // + ASSERT (FALSE); + CpuDeadLoop (); +} -- 2.7.4