From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-x244.google.com (mail-oi0-x244.google.com [IPv6:2607:f8b0:4003:c06::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 04D6021951C8D for ; Tue, 25 Apr 2017 09:36:23 -0700 (PDT) Received: by mail-oi0-x244.google.com with SMTP id m34so28208861oik.2 for ; Tue, 25 Apr 2017 09:36:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cVfEWmKIrhr6tpRJQaFmJhUfBIjwFAOKx0qakQeEmrs=; b=FMt+N4vSrwYAyvdlKST2QNRcR2XDsE6VUAuaLkT9CRQclXUrzOqrGTA2pfY9VgzAIO GYpqpk5nVcuBeQqyrNpgVQ1HLv4gQQla7EM35Qet6v8ImDoMvDK9KOJTMIFqeW6MVWvz qbxUjIDlA406z8cdw9SV5BsT8hEx2o7lSyOkaigcZcU9Pw709602cJgiW1TOJIWCUVYm HcWpYhjIXcQtqkwA4hUpzFgap8pUGreJNvvhMqL5tJasOG1U75PH31l1lwcmfEVNvtvz 2xYAtpc4r5F1n12Fvyz1MYZksejXSTN/SyJDRVxlKQLmXNWPjwvpNUevKZOx4Iuqz5ie ihDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cVfEWmKIrhr6tpRJQaFmJhUfBIjwFAOKx0qakQeEmrs=; b=NjyXmXBPu4vQTbBTX1Na0mzR53N3LPbWxlMnwHl12ON0o3CxtLYgCG7PhFwDFb711K W+9nqw/oc5Ppm7X/Hy6/FsbSRCxYb/SFkMKqVNbuTkYgxH82KHMOmxXqq/vUaM5SQLWL 6qevQy1jD8mE9tTgS9YqbaAHO8iVi032j+RGfUy+mKwPB+WGi7CFgSlZ/433P0C+cfXT 7y4t/4onnlUGnDtkDIxGBduLWBZI68V69LHdqUXaW3BYOpCikIuhxJz3BL/ZedB+IY8I Jkn9vxS9HFrJ7W3ClN3uOsv4m0ut51ss+My7tmRZF0HVuSrEoHV7rHIZeT1FBGy9hqRr Yk9A== X-Gm-Message-State: AN3rC/6L6nqwdyQ5eFOaFZq2Qgm7TPCiSfKIsQ6HRQ+nKubTs/8yJp4Y RVdTpAJOq6o2XQ== X-Received: by 10.157.13.46 with SMTP id 43mr19976113oti.5.1493138182307; Tue, 25 Apr 2017 09:36:22 -0700 (PDT) Received: from brijesh-build-machine.amd.com ([165.204.77.1]) by smtp.gmail.com with ESMTPSA id j17sm9666356ota.24.2017.04.25.09.36.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 25 Apr 2017 09:36:21 -0700 (PDT) From: Brijesh Singh To: edk2-devel@lists.01.org, lersek@redhat.com, jordan.l.justen@intel.com Cc: jiewen.yao@intel.com, leo.duran@amd.com, star.zeng@intel.com, liming.gao@intel.com, ard.biesheuvel@linaro.org, brijesh.singh@amd.com, William.Tambe@amd.com, thomas.lendacky@amd.com Date: Tue, 25 Apr 2017 12:34:21 -0400 Message-Id: <1493138064-7816-13-git-send-email-brijesh.ksingh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493138064-7816-1-git-send-email-brijesh.ksingh@gmail.com> References: <1493138064-7816-1-git-send-email-brijesh.ksingh@gmail.com> Subject: [RFC v3 12/15] OvmfPkg/QemuFwCfgLib: Implement SEV internal function for Dxe phase X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Apr 2017 16:36:23 -0000 From: Brijesh Singh When SEV is enabled, the DMA must be performed on unencrypted pages. So when get asked to perfom FWCFG DMA read or write, we allocate a intermediate (bounce buffer) unencrypted buffer and use this buffer for DMA read or write. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh --- OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf | 1 + OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c | 69 ++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf index 346bb881ffc1..8780e6bf797b 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf @@ -44,6 +44,7 @@ [Packages] [LibraryClasses] BaseLib BaseMemoryLib + BmDmaLib DebugLib IoLib MemoryAllocationLib diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c index ac05f4c347f3..b738b6ebd527 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c @@ -4,6 +4,7 @@ Copyright (C) 2013, Red Hat, Inc. Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this @@ -14,14 +15,34 @@ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/ +#include "Uefi.h" + +#include #include #include +#include +#include +#include #include "QemuFwCfgLibInternal.h" STATIC BOOLEAN mQemuFwCfgSupported = FALSE; STATIC BOOLEAN mQemuFwCfgDmaSupported; +/** + + Returns a boolean indicating whether SEV is enabled + + @retval TRUE SEV is enabled + @retval FALSE SEV is disabled +**/ +BOOLEAN +InternalQemuFwCfgSevIsEnabled ( + VOID + ) +{ + return MemEncryptSevIsEnabled (); +} /** Returns a boolean indicating if the firmware configuration interface @@ -114,3 +135,51 @@ InternalQemuFwCfgDmaIsAvailable ( { return mQemuFwCfgDmaSupported; } + +/** + Allocate a bounce buffer for SEV DMA. + + @param[in] NumPage Number of pages. + @param[out] Buffer Allocated DMA Buffer pointer + +**/ +VOID +InternalQemuFwCfgSevDmaAllocateBuffer ( + IN UINT32 NumPages, + OUT VOID **Buffer + ) +{ + EFI_STATUS Status; + + // + // Allocate DMA bounce buffer + // + Status = BmDmaAllocateBuffer (TRUE, EfiBootServicesData, NumPages, Buffer); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "SEV: Failed to allocate bounce buffer %d pages\n", NumPages)); + ASSERT_EFI_ERROR (Status); + CpuDeadLoop (); + } + + DEBUG ((DEBUG_VERBOSE, "QemuFwCfgSevDma allocate buffer 0x%Lx Pages %d\n", (UINTN)Buffer, NumPages)); +} + +/** + Free the DMA buffer allocated using InternalQemuFwCfgSevDmaAllocateBuffer + + @param[in] NumPage Number of pages. + @param[in] Buffer DMA Buffer pointer + +**/ +VOID +InternalQemuFwCfgSevDmaFreeBuffer ( + IN VOID *Buffer, + IN UINT32 NumPages + ) +{ + // + // Free the bounce buffer + // + DEBUG ((DEBUG_VERBOSE, "QemuFwCfgSevDma free buffer 0x%Lx Pages %d\n", (UINTN)Buffer, NumPages)); + BmDmaFreeBuffer (Buffer, NumPages); +} -- 2.7.4