From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-x242.google.com (mail-oi0-x242.google.com [IPv6:2607:f8b0:4003:c06::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E8AFA2193CF57 for ; Tue, 25 Apr 2017 09:36:06 -0700 (PDT) Received: by mail-oi0-x242.google.com with SMTP id w12so7956859oiw.0 for ; Tue, 25 Apr 2017 09:36:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PSghcU9EBqO5Asdtp0+Fy9FGTJj0cLZD0Ni4QztfSQI=; b=N6G9hl9U8qAgSKU/Tt2Kaq3BCdLOIw8l91TXHZPIWwU2DsnTOOst1QOxh2owFdnao1 X1kx+rZhvvhhCfWp+Dn02SAoaTknUn+/5j0Rf3dAj6R+zkW07yV8cSJTr/0o1Vl9Zwan auNVNbklMuiGqWPDPVSHVqWRE6z7lEoOg7Niy6covVSLPsORK91uig9+P3muhabtifWP riDT1Z1eBysLE2Kvli3+x7rb2pmEfpDVYjc4C2JvFB2sGFL8pq5M9n/UkQMzLN1W+rAW EsOGe0ekZ9n23WGLfLYPTsVcyxEH/05RNAyETP5azYILSXLtrDXp6aAe9LcN5xZii2vF b2ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PSghcU9EBqO5Asdtp0+Fy9FGTJj0cLZD0Ni4QztfSQI=; b=AK0+XQ5/ZvZDGaey4AnsYcBATRHBJIHKlPXiuG3EsEkQ6bVIastZuo9t8kbUvZSJTE NOrTXqfJCko0YBJIyXQawQO4UuhrElY0deuSMzoiu8MZSWydbU0N/7vXOUMSklOio/3O D8QBPuDHuYX5mduKixQpG+L4vvbHb/l8+N+2C4W7K89PF7XHFoPkkAlk+X3ymI/8LbFB NutLMVBlHuH0XfpxN/KDv+YzIZXMCfgkgXmw/jpmH0ux8YbswjjT8zVeLFh0uz4HfpYI SXUPlehROR+x1ObNH/Y1kH5Rolz0baG3/bvwmYR4d66Xces9GfYQpCBvS96X2GO+OUPn EXPQ== X-Gm-Message-State: AN3rC/7awEqm2UA4dNTLo9syRB57fx8zgpIW1T6OP60nBODVjMUmr0q3 pTHqt1Q4uErJGw== X-Received: by 10.202.62.196 with SMTP id l187mr17589041oia.132.1493138166281; Tue, 25 Apr 2017 09:36:06 -0700 (PDT) Received: from brijesh-build-machine.amd.com ([165.204.77.1]) by smtp.gmail.com with ESMTPSA id j17sm9666356ota.24.2017.04.25.09.36.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 25 Apr 2017 09:36:05 -0700 (PDT) From: Brijesh Singh To: edk2-devel@lists.01.org, lersek@redhat.com, jordan.l.justen@intel.com Cc: jiewen.yao@intel.com, leo.duran@amd.com, star.zeng@intel.com, liming.gao@intel.com, ard.biesheuvel@linaro.org, brijesh.singh@amd.com, William.Tambe@amd.com, thomas.lendacky@amd.com Date: Tue, 25 Apr 2017 12:34:11 -0400 Message-Id: <1493138064-7816-3-git-send-email-brijesh.ksingh@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493138064-7816-1-git-send-email-brijesh.ksingh@gmail.com> References: <1493138064-7816-1-git-send-email-brijesh.ksingh@gmail.com> Subject: [RFC v3 02/15] OvmfPkg/ResetVector: Set C-bit when building initial page table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Apr 2017 16:36:07 -0000 From: Brijesh Singh SEV guest VMs have the concept of private and shared memory. Private memory is encrypted with the guest-specific key, while shared memory may be encrypted with hypervisor key. Certain types of memory (namely instruction pages and guest page tables) are always treated as private memory by the hardware. The C-bit in PTE indicate whether the page is private or shared. The C-bit position for the PTE can be obtained from CPUID Fn8000_001F[EBX]. When SEV is active, the BIOS is encrypted by the Qemu launch sequence, we must set the C-bit when building the page table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh --- OvmfPkg/ResetVector/Ia32/PageTables64.asm | 70 +++++++++++++++++++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/ResetVector/Ia32/PageTables64.asm index 6201cad1f5dc..3d4b04844cdf 100644 --- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm +++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm @@ -37,9 +37,60 @@ BITS 32 PAGE_READ_WRITE + \ PAGE_PRESENT) +; Check if Secure Encrypted Virtualization (SEV) feature is enabled +; +; If SEV is enabled then EAX will be at least 32 +; If SEV is disabled then EAX will be zero. +; +CheckSevFeature: + ; CPUID will clobber EBX, ECX, EDX, save these registers + push ebx + push ecx + push edx + + ; Check if we have a valid (0x8000_001F) CPUID leaf + mov eax, 0x80000000 + cpuid + + ; This check should fail on Intel or Non SEV AMD CPUs and in future if + ; Intel CPUs supports this CPUID leaf then we are guranteed to have exact + ; same bit definition. + cmp eax, 0x8000001f + jl NoSev + + ; Check for memory encryption feature: + ; CPUID Fn8000_001F[EAX] - Bit 1 + ; + mov eax, 0x8000001f + cpuid + bt eax, 1 + jnc NoSev + + ; Check if memory encryption is enabled + ; MSR_0xC0010131 - Bit 0 (SEV enabled) + mov ecx, 0xc0010131 + rdmsr + bt eax, 0 + jnc NoSev + + ; Get pte bit position to enable memory encryption + ; CPUID Fn8000_001F[EBX] - Bits 5:0 + ; + mov eax, ebx + and eax, 0x3f + jmp SevExit + +NoSev: + xor eax, eax + +SevExit: + pop edx + pop ecx + pop ebx + OneTimeCallRet CheckSevFeature ; -; Modified: EAX, ECX +; Modified: EAX, ECX, EDX ; SetCr3ForPageTables64: @@ -60,18 +111,34 @@ clearPageTablesMemoryLoop: mov dword[ecx * 4 + PT_ADDR (0) - 4], eax loop clearPageTablesMemoryLoop + OneTimeCall CheckSevFeature + xor edx, edx + test eax, eax + jz SevNotActive + + ; If SEV is enabled, Memory encryption bit is always above 31 + sub eax, 32 + bts edx, eax + +SevNotActive: + ; ; Top level Page Directory Pointers (1 * 512GB entry) ; mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR + mov dword[PT_ADDR (4)], edx ; ; Next level Page Directory Pointers (4 * 1GB entries => 4GB) ; mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR + mov dword[PT_ADDR (0x1004)], edx mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR + mov dword[PT_ADDR (0x100C)], edx mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR + mov dword[PT_ADDR (0x1014)], edx mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR + mov dword[PT_ADDR (0x101C)], edx ; ; Page Table Entries (2048 * 2MB entries => 4GB) @@ -83,6 +150,7 @@ pageTableEntriesLoop: shl eax, 21 add eax, PAGE_2M_PDE_ATTR mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax + mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx loop pageTableEntriesLoop ; -- 2.7.4