From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-0014ca01.pphosted.com (mx0a-0014ca01.pphosted.com [208.84.65.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BC28C21A09104 for ; Tue, 23 May 2017 09:16:13 -0700 (PDT) Received: from pps.filterd (m0042385.ppops.net [127.0.0.1]) by mx0a-0014ca01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v4NGFaBi009869; Tue, 23 May 2017 09:16:12 -0700 Received: from mx-sanjose.cadence.com (mx-sanjose.Cadence.COM [158.140.2.60]) by mx0a-0014ca01.pphosted.com with ESMTP id 2amrep0058-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 23 May 2017 09:16:12 -0700 Received: from maileu3.global.cadence.com (maileu3.Cadence.COM [10.160.88.99]) by mx-sanjose.cadence.com (8.14.4/8.14.4) with ESMTP id v4NGFFsk005835 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=FAIL); Tue, 23 May 2017 09:15:16 -0700 (PDT) X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 23 May 2017 18:16:04 +0200 Received: from lvloginb.cadence.com (10.165.177.11) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Tue, 23 May 2017 18:16:03 +0200 Received: from lvloginb.cadence.com (localhost [127.0.0.1]) by lvloginb.cadence.com (8.14.4/8.14.4) with ESMTP id v4NGG2A8007492; Tue, 23 May 2017 17:16:02 +0100 Received: (from stelford@localhost) by lvloginb.cadence.com (8.14.4/8.14.4/Submit) id v4NGG1fn007482; Tue, 23 May 2017 17:16:01 +0100 From: Scott Telford To: , , Date: Tue, 23 May 2017 17:15:47 +0100 Message-ID: <1495556147-6883-1-git-send-email-stelford@cadence.com> X-Mailer: git-send-email 2.2.2 MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-Received: by mx-sanjose.cadence.com as v4NGFFsk005835 at Tue May 23 09:15:16 2017 Subject: [PATCH] Copy bus scanning workaround from ARM Juno PCIe driver. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 May 2017 16:16:13 -0000 Content-Type: text/plain Copy workaround previously in ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c:PciRbPciRead() to RootBridgeIoPciAccess(), to avoid spurious multiple detections when scanning buses. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Telford --- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index a0e7e5b..3cca3c1 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -945,6 +945,19 @@ RootBridgeIoPciAccess ( PciAddress.ExtendedRegister = PciAddress.Register; } + // The UEFI PCI enumerator scans for devices at all possible addresses, + // and ignores some PCI rules - this results in some hardware being + // detected multiple times. We work around this by faking absent + // devices + if ((PciAddress.Bus == 0) && ((PciAddress.Device != 0) || (PciAddress.Function != 0))) { + *((UINT32 *)Buffer) = 0xffffffff; + return EFI_SUCCESS; + } + if ((PciAddress.Bus == 1) && ((PciAddress.Device != 0) || (PciAddress.Function != 0))) { + *((UINT32 *)Buffer) = 0xffffffff; + return EFI_SUCCESS; + } + Address = PCI_SEGMENT_LIB_ADDRESS ( RootBridge->RootBridgeIo.SegmentNumber, PciAddress.Bus, -- 2.2.2