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Wed, 24 May 2017 23:32:58 +0000 From: Leo Duran To: CC: Leo Duran , Jordan Justen , Jeff Fan , Liming Gao , Brijesh Singh Date: Wed, 24 May 2017 18:32:47 -0500 Message-ID: <1495668768-10416-2-git-send-email-leo.duran@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495668768-10416-1-git-send-email-leo.duran@amd.com> References: <1495668768-10416-1-git-send-email-leo.duran@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM5PR15CA0024.namprd15.prod.outlook.com (10.173.207.162) To CY4PR12MB1240.namprd12.prod.outlook.com (10.168.167.15) X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PR12MB1240: X-MS-Office365-Filtering-Correlation-Id: 63092a44-e678-4e1d-7ace-08d4a2fd3684 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(48565401081)(201703131423075)(201703031133081); SRVR:CY4PR12MB1240; X-Microsoft-Exchange-Diagnostics: 1; CY4PR12MB1240; 3:k2IiCKTaT/o66BbWW0I9cT0P6mjtdPtecCVW9v99T+MpOUKOfR1E+EEswVCN1VSajMfXw05YQ6SPoq6jz1uQOFeMMlEerS+4SmNJlAhY6mWq6Wsp0KQiqv0Zi64yKOo9u/BCw+HqsejTuyaEhWRYUTgKCQy4c1ncUPD6cMAF2xYxG0fniZMFLn5pXvlrg3fiG0yPt7sEuVXESY1z1/5Ye0WgAE5SMpg47X9+lK4lDInZOVc1DYQROb5tQZmMmpcoHV+fUiwSUBDXp/bxAJloMXfBebNHtFZ30wLxBTKDDM6dQIB4BW6+t2V9e2hhGAruk/6eLgish8Iz8PGRZm4n1xlgFb4WtwI1hP6a+yTX8VM=; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 May 2017 23:33:01 -0000 Content-Type: text/plain Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/Include/Register/Amd/Cpuid.h | 265 ++++++++++++++++++++++++++++++-- 1 file changed, 256 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Amd/Cpuid.h b/UefiCpuPkg/Include/Register/Amd/Cpuid.h index 74ffb95..4a26bf7 100644 --- a/UefiCpuPkg/Include/Register/Amd/Cpuid.h +++ b/UefiCpuPkg/Include/Register/Amd/Cpuid.h @@ -7,6 +7,7 @@ not provided for that register. Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -24,8 +25,253 @@ #define __AMD_CPUID_H__ /** + CPUID Extended Processor Signature and Feature Bits - Memory Encryption Information + @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) + + @retval EAX CPUID_EXTENDED_CPU_SIG. + @retval EBX Reserved. + @retval ECX Extended Processor Signature and Feature Bits information + described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX. + @retval EDX Extended Processor Signature and Feature Bits information + described by the type CPUID_EXTENDED_CPU_SIG_EDX. + + Example usage + @code + UINT32 Eax; + CPUID_AMD_EXTENDED_CPU_SIG_ECX Ecx; + CPUID_EXTENDED_CPU_SIG_EDX Edx; + + AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32); + @endcode +**/ + +/** + CPUID AMD Extended Processor Signature and Feature Bits ECX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LAHF/SAHF available in 64-bit mode. + /// + UINT32 LAHF_SAHF:1; + /// + /// [Bit 1] Core multi-processing legacy mode. + /// + UINT32 CmpLegacy:1; + /// + /// [Bit 2] Secure Virtual Mode feature. + /// + UINT32 SVM:1; + /// + /// [Bit 3] Extended APIC register space. + /// + UINT32 ExtApicSpace:1; + /// + /// [Bit 4] LOCK MOV CR0 means MOV CR8. + /// + UINT32 AltMovCr8:1; + /// + /// [Bit 5] LZCNT instruction support. + /// + UINT32 LZCNT:1; + /// + /// [Bit 6] SSE4A instruction support. + /// + UINT32 SSE4A:1; + /// + /// [Bit 7] Misaligned SSE Mode. + /// + UINT32 MisAlignSse:1; + /// + /// [Bit 8] ThreeDNow Prefetch instructions. + /// + UINT32 PREFETCHW:1; + /// + /// [Bit 9] OS Visible Work-around support. + /// + UINT32 OSVW:1; + /// + /// [Bit 10] Instruction Based Sampling. + /// + UINT32 IBS:1; + /// + /// [Bit 11] Extened Operation Support. + /// + UINT32 XOP:1; + /// + /// [Bit 12] SKINIT and STGI support. + /// + UINT32 SKINIT:1; + /// + /// [Bit 13] Watchdog Timer support. + /// + UINT32 WDT:1; + /// + /// [Bit 14] Reserved. + /// + UINT32 Reserved1:1; + /// + /// [Bit 15] Lightweight Profiling support. + /// + UINT32 LWP:1; + /// + /// [Bit 16] 4-Operand FMA instruction support. + /// + UINT32 FMA4:1; + /// + /// [Bit 17] Translation Cache Extension. + /// + UINT32 TCE:1; + /// + /// [Bit 21:18] Reserved. + /// + UINT32 Reserved2:4; + /// + /// [Bit 22] Topology Extensions support. + /// + UINT32 TopologyExtensions:1; + /// + /// [Bit 23] Core Performance Counter Extensions. + /// + UINT32 PerfCtrExtCore:1; + /// + /// [Bit 25:24] Reserved. + /// + UINT32 Reserved3:2; + /// + /// [Bit 26] Data Breakpoint Extension. + /// + UINT32 DataBreakpointExtension:1; + /// + /// [Bit 27] Performance Time-Stamp Counter. + /// + UINT32 PerfTsc:1; + /// + /// [Bit 28] L3 Performance Counter Extensions. + /// + UINT32 PerfCtrExtL3:1; + /// + /// [Bit 29] MWAITX and MONITORX capability. + /// + UINT32 MwaitExtended:1; + /// + /// [Bit 31:30] Reserved. + /// + UINT32 Reserved4:2; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_ECX; + + +/** + CPUID AMD Processor Topology + + @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E) + + @retval EAX Extended APIC ID. + @retval EBX Core Indentifiers. + @retval ECX Node Indentifiers. + @retval EDX Reserved. + + Example usage + @code + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + + AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, &Eax, &Ebx, &Ecx, &Edx); + @endcode +**/ +#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E + +/** + CPUID AMD Processor Topology support information EAX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Extended APIC Id. + /// + UINT32 ExtendedApicId; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX; + +/** + CPUID AMD Processor Topology support information EBX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Core Id. + /// + UINT32 CoreId:8; + /// + /// [Bits 15:8] Threads per core. + /// + UINT32 ThreadsPerCore:8; + /// + /// [Bit 31:16] Reserved. + /// + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX; + +/** + CPUID AMD Processor Topology support information ECX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Node Id. + /// + UINT32 NodeId:8; + /// + /// [Bits 10:8] Nodes per processor. + /// + UINT32 NodesPerProcessor:3; + /// + /// [Bit 31:11] Reserved. + /// + UINT32 Reserved:21; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX; + + +/** + CPUID Memory Encryption Information @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F) @@ -33,8 +279,8 @@ @retval EBX If memory encryption feature is present then return the page table bit number used to enable memory encryption support and reducing of physical address space in bits. - @retval ECX Returns number of encrypted guest supported simultaneosuly. - @retval EDX Returns minimum SEV enabled and SEV disbled ASID.. + @retval ECX Returns number of encrypted guest supported simultaneously. + @retval EDX Returns minimum SEV enabled and SEV disabled ASID. Example usage @code @@ -79,7 +325,7 @@ typedef union { UINT32 SevEsBit:1; /// - /// [Bit 4:31] Reserved + /// [Bit 31:4] Reserved /// UINT32 ReservedBits:28; } Bits; @@ -99,17 +345,18 @@ typedef union { /// struct { /// - /// [Bit 0:5] Page table bit number used to enable memory encryption + /// [Bit 5:0] Page table bit number used to enable memory encryption /// UINT32 PtePosBits:6; /// - /// [Bit 6:11] Reduction of system physical address space bits when memory encryption is enabled + /// [Bit 11:6] Reduction of system physical address space bits when + /// memory encryption is enabled /// UINT32 ReducedPhysBits:5; /// - /// [Bit 12:31] Reserved + /// [Bit 31:12] Reserved /// UINT32 ReservedBits:21; } Bits; @@ -129,7 +376,7 @@ typedef union { /// struct { /// - /// [Bit 0:31] Number of encrypted guest supported simultaneously + /// [Bit 31:0] Number of encrypted guest supported simultaneously /// UINT32 NumGuests; } Bits; @@ -149,7 +396,7 @@ typedef union { /// struct { /// - /// [Bit 0:31] Minimum SEV enabled, SEV-ES disabled ASID + /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID /// UINT32 MinAsid; } Bits; -- 2.7.4