* [PATCH 1/2] UefiCpuPkg: Add CPUID definitions for AMD.
2017-05-24 23:32 [PATCH 0/2] UefiCpuPkg: Add CPUID support for AMD Leo Duran
@ 2017-05-24 23:32 ` Leo Duran
2017-05-24 23:32 ` [PATCH 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD Leo Duran
1 sibling, 0 replies; 3+ messages in thread
From: Leo Duran @ 2017-05-24 23:32 UTC (permalink / raw)
To: edk2-devel; +Cc: Leo Duran, Jordan Justen, Jeff Fan, Liming Gao, Brijesh Singh
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
UefiCpuPkg/Include/Register/Amd/Cpuid.h | 265 ++++++++++++++++++++++++++++++--
1 file changed, 256 insertions(+), 9 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Amd/Cpuid.h b/UefiCpuPkg/Include/Register/Amd/Cpuid.h
index 74ffb95..4a26bf7 100644
--- a/UefiCpuPkg/Include/Register/Amd/Cpuid.h
+++ b/UefiCpuPkg/Include/Register/Amd/Cpuid.h
@@ -7,6 +7,7 @@
not provided for that register.
Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
+
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License which accompanies this
distribution. The full text of the license may be found at
@@ -24,8 +25,253 @@
#define __AMD_CPUID_H__
/**
+ CPUID Extended Processor Signature and Feature Bits
- Memory Encryption Information
+ @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
+
+ @retval EAX CPUID_EXTENDED_CPU_SIG.
+ @retval EBX Reserved.
+ @retval ECX Extended Processor Signature and Feature Bits information
+ described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
+ @retval EDX Extended Processor Signature and Feature Bits information
+ described by the type CPUID_EXTENDED_CPU_SIG_EDX.
+
+ <b>Example usage</b>
+ @code
+ UINT32 Eax;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX Ecx;
+ CPUID_EXTENDED_CPU_SIG_EDX Edx;
+
+ AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
+ @endcode
+**/
+
+/**
+ CPUID AMD Extended Processor Signature and Feature Bits ECX for CPUID leaf
+ #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] LAHF/SAHF available in 64-bit mode.
+ ///
+ UINT32 LAHF_SAHF:1;
+ ///
+ /// [Bit 1] Core multi-processing legacy mode.
+ ///
+ UINT32 CmpLegacy:1;
+ ///
+ /// [Bit 2] Secure Virtual Mode feature.
+ ///
+ UINT32 SVM:1;
+ ///
+ /// [Bit 3] Extended APIC register space.
+ ///
+ UINT32 ExtApicSpace:1;
+ ///
+ /// [Bit 4] LOCK MOV CR0 means MOV CR8.
+ ///
+ UINT32 AltMovCr8:1;
+ ///
+ /// [Bit 5] LZCNT instruction support.
+ ///
+ UINT32 LZCNT:1;
+ ///
+ /// [Bit 6] SSE4A instruction support.
+ ///
+ UINT32 SSE4A:1;
+ ///
+ /// [Bit 7] Misaligned SSE Mode.
+ ///
+ UINT32 MisAlignSse:1;
+ ///
+ /// [Bit 8] ThreeDNow Prefetch instructions.
+ ///
+ UINT32 PREFETCHW:1;
+ ///
+ /// [Bit 9] OS Visible Work-around support.
+ ///
+ UINT32 OSVW:1;
+ ///
+ /// [Bit 10] Instruction Based Sampling.
+ ///
+ UINT32 IBS:1;
+ ///
+ /// [Bit 11] Extened Operation Support.
+ ///
+ UINT32 XOP:1;
+ ///
+ /// [Bit 12] SKINIT and STGI support.
+ ///
+ UINT32 SKINIT:1;
+ ///
+ /// [Bit 13] Watchdog Timer support.
+ ///
+ UINT32 WDT:1;
+ ///
+ /// [Bit 14] Reserved.
+ ///
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 15] Lightweight Profiling support.
+ ///
+ UINT32 LWP:1;
+ ///
+ /// [Bit 16] 4-Operand FMA instruction support.
+ ///
+ UINT32 FMA4:1;
+ ///
+ /// [Bit 17] Translation Cache Extension.
+ ///
+ UINT32 TCE:1;
+ ///
+ /// [Bit 21:18] Reserved.
+ ///
+ UINT32 Reserved2:4;
+ ///
+ /// [Bit 22] Topology Extensions support.
+ ///
+ UINT32 TopologyExtensions:1;
+ ///
+ /// [Bit 23] Core Performance Counter Extensions.
+ ///
+ UINT32 PerfCtrExtCore:1;
+ ///
+ /// [Bit 25:24] Reserved.
+ ///
+ UINT32 Reserved3:2;
+ ///
+ /// [Bit 26] Data Breakpoint Extension.
+ ///
+ UINT32 DataBreakpointExtension:1;
+ ///
+ /// [Bit 27] Performance Time-Stamp Counter.
+ ///
+ UINT32 PerfTsc:1;
+ ///
+ /// [Bit 28] L3 Performance Counter Extensions.
+ ///
+ UINT32 PerfCtrExtL3:1;
+ ///
+ /// [Bit 29] MWAITX and MONITORX capability.
+ ///
+ UINT32 MwaitExtended:1;
+ ///
+ /// [Bit 31:30] Reserved.
+ ///
+ UINT32 Reserved4:2;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_ECX;
+
+
+/**
+ CPUID AMD Processor Topology
+
+ @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)
+
+ @retval EAX Extended APIC ID.
+ @retval EBX Core Indentifiers.
+ @retval ECX Node Indentifiers.
+ @retval EDX Reserved.
+
+ <b>Example usage</b>
+ @code
+ UINT32 Eax;
+ UINT32 Ebx;
+ UINT32 Ecx;
+ UINT32 Edx;
+
+ AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, &Eax, &Ebx, &Ecx, &Edx);
+ @endcode
+**/
+#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E
+
+/**
+ CPUID AMD Processor Topology support information EAX for CPUID leaf
+ #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 31:0] Extended APIC Id.
+ ///
+ UINT32 ExtendedApicId;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;
+
+/**
+ CPUID AMD Processor Topology support information EBX for CPUID leaf
+ #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] Core Id.
+ ///
+ UINT32 CoreId:8;
+ ///
+ /// [Bits 15:8] Threads per core.
+ ///
+ UINT32 ThreadsPerCore:8;
+ ///
+ /// [Bit 31:16] Reserved.
+ ///
+ UINT32 Reserved:16;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;
+
+/**
+ CPUID AMD Processor Topology support information ECX for CPUID leaf
+ #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] Node Id.
+ ///
+ UINT32 NodeId:8;
+ ///
+ /// [Bits 10:8] Nodes per processor.
+ ///
+ UINT32 NodesPerProcessor:3;
+ ///
+ /// [Bit 31:11] Reserved.
+ ///
+ UINT32 Reserved:21;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;
+
+
+/**
+ CPUID Memory Encryption Information
@param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)
@@ -33,8 +279,8 @@
@retval EBX If memory encryption feature is present then return
the page table bit number used to enable memory encryption support
and reducing of physical address space in bits.
- @retval ECX Returns number of encrypted guest supported simultaneosuly.
- @retval EDX Returns minimum SEV enabled and SEV disbled ASID..
+ @retval ECX Returns number of encrypted guest supported simultaneously.
+ @retval EDX Returns minimum SEV enabled and SEV disabled ASID.
<b>Example usage</b>
@code
@@ -79,7 +325,7 @@ typedef union {
UINT32 SevEsBit:1;
///
- /// [Bit 4:31] Reserved
+ /// [Bit 31:4] Reserved
///
UINT32 ReservedBits:28;
} Bits;
@@ -99,17 +345,18 @@ typedef union {
///
struct {
///
- /// [Bit 0:5] Page table bit number used to enable memory encryption
+ /// [Bit 5:0] Page table bit number used to enable memory encryption
///
UINT32 PtePosBits:6;
///
- /// [Bit 6:11] Reduction of system physical address space bits when memory encryption is enabled
+ /// [Bit 11:6] Reduction of system physical address space bits when
+ /// memory encryption is enabled
///
UINT32 ReducedPhysBits:5;
///
- /// [Bit 12:31] Reserved
+ /// [Bit 31:12] Reserved
///
UINT32 ReservedBits:21;
} Bits;
@@ -129,7 +376,7 @@ typedef union {
///
struct {
///
- /// [Bit 0:31] Number of encrypted guest supported simultaneously
+ /// [Bit 31:0] Number of encrypted guest supported simultaneously
///
UINT32 NumGuests;
} Bits;
@@ -149,7 +396,7 @@ typedef union {
///
struct {
///
- /// [Bit 0:31] Minimum SEV enabled, SEV-ES disabled ASID
+ /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID
///
UINT32 MinAsid;
} Bits;
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
2017-05-24 23:32 [PATCH 0/2] UefiCpuPkg: Add CPUID support for AMD Leo Duran
2017-05-24 23:32 ` [PATCH 1/2] UefiCpuPkg: Add CPUID definitions " Leo Duran
@ 2017-05-24 23:32 ` Leo Duran
1 sibling, 0 replies; 3+ messages in thread
From: Leo Duran @ 2017-05-24 23:32 UTC (permalink / raw)
To: edk2-devel; +Cc: Leo Duran, Jordan Justen, Jeff Fan, Liming Gao, Brijesh Singh
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 85 +++++++++++++---------
.../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 85 +++++++++++++---------
2 files changed, 98 insertions(+), 72 deletions(-)
mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
old mode 100644
new mode 100755
index f81bbb2..da45d7a
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -4,6 +4,8 @@
This local APIC library instance supports xAPIC mode only.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -15,6 +17,7 @@
**/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -966,20 +969,22 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -1002,20 +1007,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1030,8 +1031,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1061,26 +1060,40 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
- //
- // Must be a single-core processor.
- //
- MaxCoresPerPackage = 1;
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-thread-per-core processor.
+ //
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
*Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index e690d2a..a240a44 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -5,6 +5,8 @@
which have xAPIC and x2APIC modes.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,6 +18,7 @@
**/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -1061,20 +1064,22 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -1097,20 +1102,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1125,8 +1126,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1156,26 +1155,40 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
- //
- // Must be a single-core processor.
- //
- MaxCoresPerPackage = 1;
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-thread-per-core processor.
+ //
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
*Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread