From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx-sanjose5.cadence.com (keymaster.Cadence.COM [158.140.2.26]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1C62021A6F106 for ; Mon, 5 Jun 2017 03:49:48 -0700 (PDT) Received: from maileu3.global.cadence.com (maileu3.Cadence.COM [10.160.88.99]) by mx-sanjose5.cadence.com (8.13.8+Sun/8.14.4) with ESMTP id v55Aonkd028201; Mon, 5 Jun 2017 03:50:49 -0700 (PDT) X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 5 Jun 2017 12:50:43 +0200 Received: from lvloginb.cadence.com (10.165.177.11) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Mon, 5 Jun 2017 12:50:43 +0200 Received: from lvloginb.cadence.com (localhost [127.0.0.1]) by lvloginb.cadence.com (8.14.4/8.14.4) with ESMTP id v55AogLX000539; Mon, 5 Jun 2017 11:50:42 +0100 Received: (from stelford@localhost) by lvloginb.cadence.com (8.14.4/8.14.4/Submit) id v55AofEm032655; Mon, 5 Jun 2017 11:50:41 +0100 From: Scott Telford To: , , , , , Date: Mon, 5 Jun 2017 11:50:22 +0100 Message-ID: <1496659828-28702-1-git-send-email-stelford@cadence.com> X-Mailer: git-send-email 2.2.2 MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com Subject: [staging/cadence-aarch64 PATCH v2 0/6] CadencePkg: Add package for Cadence hardware IP support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Jun 2017 10:49:48 -0000 Content-Type: text/plain Add CadencePkg, which includes support for the Cadence Configurable System Platform (CSP) with a single ARM Cortex-A53 and GIC-500. Also include driver libraries for the Cadence PCIe Root Complex and Cadence UART. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Telford Scott Telford (6): CadencePkg: Add libraries for Cadence CSP platform. CadencePkg: Add library for Cadence UART. CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex. CadencePkg: Add SEC phase implementation for Cadence CSP platform. CadencePkg: Add ACPI tables for Cadence CSP platform. CadencePkg: Add .dsc, .fdf and .dec files for Cadence CSP platform. CadencePkg/AcpiTables/AcpiTables.inf | 49 ++ CadencePkg/AcpiTables/CspPlatform.h | 46 ++ CadencePkg/AcpiTables/Dsdt.asl | 338 ++++++++++ CadencePkg/AcpiTables/Fadt.aslc | 87 +++ CadencePkg/AcpiTables/Gtdt.aslc | 80 +++ CadencePkg/AcpiTables/Madt.aslc | 71 ++ CadencePkg/AcpiTables/Mcfg.aslc | 76 +++ CadencePkg/AcpiTables/Spcr.aslc | 89 +++ CadencePkg/CadenceCsp.dsc | 711 +++++++++++++++++++++ CadencePkg/CadenceCsp.fdf | 410 ++++++++++++ CadencePkg/CadenceCspPkg.dec | 60 ++ CadencePkg/Include/Library/CspSerialPortLib.h | 86 +++ CadencePkg/Include/Library/CspSysReg.h | 37 ++ .../CadenceCspLib/AArch64/ArmPlatformHelper.S | 62 ++ CadencePkg/Library/CadenceCspLib/CadenceCspLib.c | 135 ++++ CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf | 76 +++ .../Library/CadenceCspLib/CadenceCspLibMem.c | 145 +++++ .../Library/CadenceCspLib/CadenceCspLibSec.inf | 52 ++ .../CadenceCspResetSystemLib.c | 83 +++ .../CadenceCspResetSystemLib.inf | 40 ++ .../Library/CadenceCspSecLib/AArch64/CspBoot.S | 63 ++ .../Library/CadenceCspSecLib/AArch64/GicV3.S | 70 ++ .../Library/CadenceCspSecLib/CadenceCspSecLib.inf | 44 ++ CadencePkg/Library/CadenceCspSecLib/CspSec.c | 79 +++ .../CadenceCspSerialPortLib/CspSerialPortLib.c | 525 +++++++++++++++ .../CadenceCspSerialPortLib/CspSerialPortLib.inf | 52 ++ .../CadenceCspSerialPortLib/CspSerialPortLib.uni | Bin 0 -> 1622 bytes .../Library/CadencePciHostBridgeLib/CdnsPci.c | 103 +++ .../Library/CadencePciHostBridgeLib/CdnsPci.h | 85 +++ .../CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c | 189 ++++++ .../CdnsPciHostBridgeLib.inf | 77 +++ CadencePkg/Sec/AArch64/Arch.c | 25 + CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S | 27 + CadencePkg/Sec/AArch64/Helper.S | 93 +++ CadencePkg/Sec/AArch64/SecEntryPoint.S | 139 ++++ CadencePkg/Sec/Sec.c | 335 ++++++++++ CadencePkg/Sec/Sec.inf | 85 +++ CadencePkg/Sec/SecInternal.h | 105 +++ 38 files changed, 4829 insertions(+) create mode 100644 CadencePkg/AcpiTables/AcpiTables.inf create mode 100644 CadencePkg/AcpiTables/CspPlatform.h create mode 100644 CadencePkg/AcpiTables/Dsdt.asl create mode 100644 CadencePkg/AcpiTables/Fadt.aslc create mode 100644 CadencePkg/AcpiTables/Gtdt.aslc create mode 100644 CadencePkg/AcpiTables/Madt.aslc create mode 100644 CadencePkg/AcpiTables/Mcfg.aslc create mode 100644 CadencePkg/AcpiTables/Spcr.aslc create mode 100644 CadencePkg/CadenceCsp.dsc create mode 100644 CadencePkg/CadenceCsp.fdf create mode 100644 CadencePkg/CadenceCspPkg.dec create mode 100644 CadencePkg/Include/Library/CspSerialPortLib.h create mode 100644 CadencePkg/Include/Library/CspSysReg.h create mode 100644 CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.c create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S create mode 100644 CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf create mode 100644 CadencePkg/Library/CadenceCspSecLib/CspSec.c create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf create mode 100644 CadencePkg/Sec/AArch64/Arch.c create mode 100644 CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S create mode 100644 CadencePkg/Sec/AArch64/Helper.S create mode 100644 CadencePkg/Sec/AArch64/SecEntryPoint.S create mode 100644 CadencePkg/Sec/Sec.c create mode 100644 CadencePkg/Sec/Sec.inf create mode 100644 CadencePkg/Sec/SecInternal.h -- 2.2.2