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Fri, 16 Jun 2017 22:57:11 +0000 From: Leo Duran To: edk2-devel@lists.01.org Cc: Leo Duran , Jordan Justen , Jeff Fan , Liming Gao , Brijesh Singh Date: Fri, 16 Jun 2017 17:57:00 -0500 Message-Id: <1497653820-15192-3-git-send-email-leo.duran@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497653820-15192-1-git-send-email-leo.duran@amd.com> References: <1497653820-15192-1-git-send-email-leo.duran@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.78.1] X-ClientProxiedBy: MWHPR1701CA0003.namprd17.prod.outlook.com (10.172.58.13) To DM5PR12MB1244.namprd12.prod.outlook.com (10.168.237.135) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 015f7af9-9694-4546-c476-08d4b50b0655 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(48565401081)(201703131423075)(201703031133081); SRVR:DM5PR12MB1244; X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1244; 3:LnfG7bRXl/DTuzOF81uc+xqOHxkhRoQCvOoALkSvUX4HNDcGL4SgCThCmv/CEVxS7U3dWzMSpyAHZo62E62qpMArRhNZfuIBWCpPmpCc2M1QNt9cAVu7y3H6441sFOjTTQTX2/b2k2HSJ1Qqp33VNobwn3PFpttVVkbIaqqAiYwJVWjd0W6QaIocSrOCUvuRZI3b5fFexknJQ7Letpeq6OSJ0EeWd8whptBkIOIJI2y8oBgn/pjAGpcXQvT59r7aBWjVak7hSjj4bmJp/1uanIWOq6iy02aNfNToWixv2tXppWg1BerInTzTCP5ECZLTFYgRxNgjlxHZUrK/Wg8f+RaENUAfvPVMlUf0rzUxijI=; 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DM5PR12MB1244; 20:GJpy4JGcYTpH8Zny6XfoFQQxuHon9Kp5Zt352+ehCCupM5jugkMLEpxu7odrUDCCoveQwh3tWiokY9h08RrRs0paxtNoXtijRPiXxgydH+V3J27AhUv5b5s7TOzZH8vfqrevLjI6OrAtZ9F9K/XmhZpPAHW9JFIqUY68FTwlSOTZ20KTPJiWPu3Ae4nkyVFmCYzCM9zxXG5NViftC0b8sSlUnJtxzQKmbf4grCDQkgqEBwwv0AlmYH9S3qQ4OPvO X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2017 22:57:11.3353 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1244 Subject: [PATCH v4 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Jun 2017 22:55:54 -0000 Content-Type: text/plain Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 140 ++++++++++++++++----- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 140 ++++++++++++++++----- 2 files changed, 216 insertions(+), 64 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c index f81bbb2..898d844 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -4,6 +4,8 @@ This local APIC library instance supports xAPIC mode only. Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Inc. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -15,6 +17,7 @@ **/ #include +#include #include #include @@ -966,20 +969,33 @@ GetProcessorLocationByApicId ( OUT UINT32 *Thread OPTIONAL ) { - BOOLEAN TopologyLeafSupported; - UINTN ThreadBits; - UINTN CoreBits; - CPUID_VERSION_INFO_EBX VersionInfoEbx; - CPUID_VERSION_INFO_EDX VersionInfoEdx; - CPUID_CACHE_PARAMS_EAX CacheParamsEax; - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; + BOOLEAN TopologyLeafSupported; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; + UINT32 SignatureEbx; + UINT32 SignatureEcx; + UINT32 SignatureEdx; + UINT32 MaxStandardCpuIdIndex; + UINT32 MaxExtendedCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + UINT32 MaxThreadPerPackageMask; + UINT32 ActualThreadPerPackageMask; + UINT32 MaxCoresPerNode; + UINT32 CorePerNodeMask; + UINT32 ApicIdShift; + UINTN ThreadBits; + UINTN CoreBits; // // Check if the processor is capable of supporting more than one logical processor. @@ -987,10 +1003,10 @@ GetProcessorLocationByApicId ( AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT == 0) { if (Thread != NULL) { - *Thread = 0; + *Thread = 0; } if (Core != NULL) { - *Core = 0; + *Core = 0; } if (Package != NULL) { *Package = 0; @@ -998,24 +1014,24 @@ GetProcessorLocationByApicId ( return; } + // + // Assume three-level mapping of APIC ID: Package|Core|Thread. + // ThreadBits = 0; CoreBits = 0; // - // Assume three-level mapping of APIC ID: Package:Core:SMT. + // Get max index of CPUID and vendor's signature // - TopologyLeafSupported = FALSE; - - // - // Get the max index of basic CPUID - // - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, &SignatureEbx, &SignatureEcx, &SignatureEdx); + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL); // // If the extended topology enumeration leaf is available, it // is the preferred mechanism for enumerating topology. // - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { + TopologyLeafSupported = FALSE; + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { AsmCpuidEx( CPUID_EXTENDED_TOPOLOGY, 0, @@ -1065,27 +1081,87 @@ GetProcessorLocationByApicId ( } if (!TopologyLeafSupported) { + // + // Get logical processor count + // AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL); - MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; + + // + // Assume single-core processor + // + MaxCoresPerPackage = 1; + + // + // Check for topology extensions on AMD processor + // + if (SignatureEbx == CPUID_SIGNATURE_GENUINE_AMD_EBX && + SignatureEcx == CPUID_SIGNATURE_GENUINE_AMD_ECX && + SignatureEdx == CPUID_SIGNATURE_GENUINE_AMD_EDX) { + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) { + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL); + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) { + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, + &AmdProcessorTopologyEcx.Uint32, NULL); + // + // Get cores per processor package + // + MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); + + // + // Account for actual thread count (e.g., SMT disabled) + // + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL); + MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize; + ActualThreadPerPackageMask = 1; + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) { + ActualThreadPerPackageMask <<= 1; + } + + // + // Adjust APIC Id to report concatenation of Package|Core|Thread. + // + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { + MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1); + + CorePerNodeMask = 1; + while (CorePerNodeMask < MaxCoresPerNode) { + CorePerNodeMask <<= 1; + } + CorePerNodeMask -= 1; + + ApicIdShift = 0; + do { + ApicIdShift += 1; + ActualThreadPerPackageMask <<= 1; + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); + + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask); + } + } + } } else { // - // Must be a single-core processor. + // Extract core count based on CACHE information // - MaxCoresPerPackage = 1; + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL); + if (CacheParamsEax.Uint32 != 0) { + MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; + } + } } ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); + } if (Thread != NULL) { - *Thread = InitialApicId & ((1 << ThreadBits) - 1); + *Thread = InitialApicId & ((1 << ThreadBits) - 1); } if (Core != NULL) { - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); } if (Package != NULL) { *Package = (InitialApicId >> (ThreadBits + CoreBits)); diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index e690d2a..9d3b82f 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -5,6 +5,8 @@ which have xAPIC and x2APIC modes. Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Inc. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -16,6 +18,7 @@ **/ #include +#include #include #include @@ -1061,20 +1064,33 @@ GetProcessorLocationByApicId ( OUT UINT32 *Thread OPTIONAL ) { - BOOLEAN TopologyLeafSupported; - UINTN ThreadBits; - UINTN CoreBits; - CPUID_VERSION_INFO_EBX VersionInfoEbx; - CPUID_VERSION_INFO_EDX VersionInfoEdx; - CPUID_CACHE_PARAMS_EAX CacheParamsEax; - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; + BOOLEAN TopologyLeafSupported; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; + UINT32 SignatureEbx; + UINT32 SignatureEcx; + UINT32 SignatureEdx; + UINT32 MaxStandardCpuIdIndex; + UINT32 MaxExtendedCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + UINT32 MaxThreadPerPackageMask; + UINT32 ActualThreadPerPackageMask; + UINT32 MaxCoresPerNode; + UINT32 CorePerNodeMask; + UINT32 ApicIdShift; + UINTN ThreadBits; + UINTN CoreBits; // // Check if the processor is capable of supporting more than one logical processor. @@ -1082,10 +1098,10 @@ GetProcessorLocationByApicId ( AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT == 0) { if (Thread != NULL) { - *Thread = 0; + *Thread = 0; } if (Core != NULL) { - *Core = 0; + *Core = 0; } if (Package != NULL) { *Package = 0; @@ -1093,24 +1109,24 @@ GetProcessorLocationByApicId ( return; } + // + // Assume three-level mapping of APIC ID: Package|Core|Thread. + // ThreadBits = 0; CoreBits = 0; // - // Assume three-level mapping of APIC ID: Package:Core:SMT. + // Get max index of CPUID and vendor's signature // - TopologyLeafSupported = FALSE; - - // - // Get the max index of basic CPUID - // - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, &SignatureEbx, &SignatureEcx, &SignatureEdx); + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL); // // If the extended topology enumeration leaf is available, it // is the preferred mechanism for enumerating topology. // - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { + TopologyLeafSupported = FALSE; + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { AsmCpuidEx( CPUID_EXTENDED_TOPOLOGY, 0, @@ -1160,27 +1176,87 @@ GetProcessorLocationByApicId ( } if (!TopologyLeafSupported) { + // + // Get logical processor count + // AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL); - MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; + + // + // Assume single-core processor + // + MaxCoresPerPackage = 1; + + // + // Check for topology extensions on AMD processor + // + if (SignatureEbx == CPUID_SIGNATURE_GENUINE_AMD_EBX && + SignatureEcx == CPUID_SIGNATURE_GENUINE_AMD_ECX && + SignatureEdx == CPUID_SIGNATURE_GENUINE_AMD_EDX) { + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) { + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL); + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) { + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, + &AmdProcessorTopologyEcx.Uint32, NULL); + // + // Get cores per processor package + // + MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); + + // + // Account for actual thread count (e.g., SMT disabled) + // + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL); + MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize; + ActualThreadPerPackageMask = 1; + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) { + ActualThreadPerPackageMask <<= 1; + } + + // + // Adjust APIC Id to report concatenation of Package|Core|Thread. + // + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { + MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1); + + CorePerNodeMask = 1; + while (CorePerNodeMask < MaxCoresPerNode) { + CorePerNodeMask <<= 1; + } + CorePerNodeMask -= 1; + + ApicIdShift = 0; + do { + ApicIdShift += 1; + ActualThreadPerPackageMask <<= 1; + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); + + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask); + } + } + } } else { // - // Must be a single-core processor. + // Extract core count based on CACHE information // - MaxCoresPerPackage = 1; + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL); + if (CacheParamsEax.Uint32 != 0) { + MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; + } + } } ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); + } if (Thread != NULL) { - *Thread = InitialApicId & ((1 << ThreadBits) - 1); + *Thread = InitialApicId & ((1 << ThreadBits) - 1); } if (Core != NULL) { - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); } if (Package != NULL) { *Package = (InitialApicId >> (ThreadBits + CoreBits)); -- 2.7.4