From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B476921A07AB5 for ; Tue, 27 Jun 2017 19:41:55 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jun 2017 19:43:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,273,1496127600"; d="scan'208";a="1165408712" Received: from shwdeopenpsi114.ccr.corp.intel.com ([10.239.157.135]) by fmsmga001.fm.intel.com with ESMTP; 27 Jun 2017 19:43:25 -0700 From: Dandan Bi To: edk2-devel@lists.01.org Cc: Brijesh Singh , Jeff Fan Date: Wed, 28 Jun 2017 10:42:38 +0800 Message-Id: <1498617758-21960-1-git-send-email-dandan.bi@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.1 Subject: [patch] UefiCpuPkg: Fix coding style issues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Jun 2017 02:41:55 -0000 Cc: Brijesh Singh Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi --- UefiCpuPkg/Include/Register/Amd/Fam17Msr.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h b/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h index 2c5d973..9a79de1 100644 --- a/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h +++ b/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h @@ -18,12 +18,12 @@ @par Specification Reference: AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34 **/ -#ifndef __FAM17_MSR_H -#define __FAM17_MSR_H +#ifndef __FAM17_MSR_H__ +#define __FAM17_MSR_H__ /** Secure Encrypted Virtualization (SEV) status register **/ -- 1.9.5.msysgit.1