From: Abner Chang <abner.chang@hpe.com>
To: edk2-devel@lists.01.org
Subject: [staging/branch RISC-V PATCH 3/4] BaseTools: Add more RISC-V relocation types.
Date: Tue, 4 Jul 2017 13:29:23 +0800 [thread overview]
Message-ID: <1499146164-26231-4-git-send-email-abner.chang@hpe.com> (raw)
In-Reply-To: <1499146164-26231-1-git-send-email-abner.chang@hpe.com>
Add more RISC-V relocation types to prevent from errors happen
when build RISC-V edk2 port by RISC-V gcc 7.1.1.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
BaseTools/Source/C/GenFw/Elf64Convert.c | 18 +++++++++++++++++-
BaseTools/Source/C/GenFw/elf_common.h | 10 +++++++++-
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 9deb846..4857485 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -3,7 +3,7 @@ Elf64 convert solution
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
-Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2016-2017, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License which accompanies this
@@ -953,6 +953,14 @@ WriteSections64 (
case R_RISCV_GPREL_I:
case R_RISCV_GPREL_S:
case R_RISCV_CALL:
+ case R_RISCV_RVC_BRANCH:
+ case R_RISCV_RVC_JUMP:
+ case R_RISCV_RELAX:
+ case R_RISCV_SUB6:
+ case R_RISCV_SET6:
+ case R_RISCV_SET8:
+ case R_RISCV_SET16:
+ case R_RISCV_SET32:
break;
default:
@@ -1129,6 +1137,14 @@ WriteRelocations64 (
case R_RISCV_GPREL_I:
case R_RISCV_GPREL_S:
case R_RISCV_CALL:
+ case R_RISCV_RVC_BRANCH:
+ case R_RISCV_RVC_JUMP:
+ case R_RISCV_RELAX:
+ case R_RISCV_SUB6:
+ case R_RISCV_SET6:
+ case R_RISCV_SET8:
+ case R_RISCV_SET16:
+ case R_RISCV_SET32:
break;
default:
diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/GenFw/elf_common.h
index 0ff9720..65ec5f7 100644
--- a/BaseTools/Source/C/GenFw/elf_common.h
+++ b/BaseTools/Source/C/GenFw/elf_common.h
@@ -3,7 +3,7 @@ Ported ELF include files from FreeBSD
Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
-Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2016-2017, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -1109,4 +1109,12 @@ typedef struct {
#define R_RISCV_RVC_LUI 46
#define R_RISCV_GPREL_I 47
#define R_RISCV_GPREL_S 48
+#define R_RISCV_TPREL_I 49
+#define R_RISCV_TPREL_S 50
+#define R_RISCV_RELAX 51
+#define R_RISCV_SUB6 52
+#define R_RISCV_SET6 53
+#define R_RISCV_SET8 54
+#define R_RISCV_SET16 55
+#define R_RISCV_SET32 56
#endif /* !_SYS_ELF_COMMON_H_ */
--
2.7.4
next prev parent reply other threads:[~2017-07-04 5:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-04 5:29 [staging/branch RISC-V PATCH 0/4] RISC-V edk2 port GCC 7.1.1 Abner Chang
2017-07-04 5:29 ` [staging/branch RISC-V PATCH 1/4] RiscVPkg/Sec: Use MRET in machine trap handler Abner Chang
2017-07-04 5:29 ` [staging/branch RISC-V PATCH 2/4] BaseTools: Support RISC-V GCC 7.1.1 Abner Chang
2017-07-04 5:29 ` Abner Chang [this message]
2017-07-04 5:29 ` [staging/branch RISC-V PATCH 4/4] RiscVVirtPkg: Update README file Abner Chang
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