* [staging/branch RISC-V PATCH 1/4] RiscVPkg/Sec: Use MRET in machine trap handler.
2017-07-04 5:29 [staging/branch RISC-V PATCH 0/4] RISC-V edk2 port GCC 7.1.1 Abner Chang
@ 2017-07-04 5:29 ` Abner Chang
2017-07-04 5:29 ` [staging/branch RISC-V PATCH 2/4] BaseTools: Support RISC-V GCC 7.1.1 Abner Chang
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Abner Chang @ 2017-07-04 5:29 UTC (permalink / raw)
To: edk2-devel
Use MRET(Machine Mode Trap-Return) instead of SRET(Supervisor Mode
Trap-Return) to return from machine mode trap handler.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/Universal/Sec/Riscv64/SecEntry.s | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/RiscVPkg/Universal/Sec/Riscv64/SecEntry.s b/RiscVPkg/Universal/Sec/Riscv64/SecEntry.s
index f13596d..cc4ca6d 100644
--- a/RiscVPkg/Universal/Sec/Riscv64/SecEntry.s
+++ b/RiscVPkg/Universal/Sec/Riscv64/SecEntry.s
@@ -2,7 +2,7 @@
//
// RISC-V Sec module.
//
-// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2016-2017, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
@@ -77,33 +77,33 @@ ASM_PFX(_ModuleEntryPoint):
//
ASM_PFX(TrapFromUserModeHandler):
call RiscVUserModeTrapHandler
- eret
+ mret
//
//Supervisor mode trap handler.
//
ASM_PFX(TrapFromSupervisorModeHandler):
call RiscVSupervisorModeTrapHandler
- eret
+ mret
//
// Hypervisor mode trap handler.
//
ASM_PFX(TrapFromHypervisorModeHandler):
call RiscVHypervisorModeTrapHandler
- eret
+ mret
//
// Machine mode trap handler.
//
ASM_PFX(TrapFromMachineModeHandler):
call RiscVMachineModeTrapHandler
- eret
+ mret
//
// NMI trap handler.
//
ASM_PFX(NmiHandler):
call RiscVNmiHandler
- eret
+ mret
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* [staging/branch RISC-V PATCH 2/4] BaseTools: Support RISC-V GCC 7.1.1.
2017-07-04 5:29 [staging/branch RISC-V PATCH 0/4] RISC-V edk2 port GCC 7.1.1 Abner Chang
2017-07-04 5:29 ` [staging/branch RISC-V PATCH 1/4] RiscVPkg/Sec: Use MRET in machine trap handler Abner Chang
@ 2017-07-04 5:29 ` Abner Chang
2017-07-04 5:29 ` [staging/branch RISC-V PATCH 3/4] BaseTools: Add more RISC-V relocation types Abner Chang
2017-07-04 5:29 ` [staging/branch RISC-V PATCH 4/4] RiscVVirtPkg: Update README file Abner Chang
3 siblings, 0 replies; 5+ messages in thread
From: Abner Chang @ 2017-07-04 5:29 UTC (permalink / raw)
To: edk2-devel
Add build tool definition for RISC-V GCC 7.1.1.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
BaseTools/Conf/tools_def.template | 85 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 84 insertions(+), 1 deletion(-)
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 2ae009e..682d8b3 100644
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -3,7 +3,7 @@
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR>
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+# (C) Copyright 2016-2017 Hewlett Packard Enterprise Development LP<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -204,6 +204,8 @@ DEFINE GCC49_X64_PREFIX = ENV(GCC49_BIN)
#
DEFINE GCC53RISCV_RISCV32_PREFIX = ~/riscv/bin/
DEFINE GCC53RISCV_RISCV64_PREFIX = ~/riscv/bin/
+DEFINE GCC711RISCV_RISCV32_PREFIX = ~/riscv/bin/
+DEFINE GCC711RISCV_RISCV64_PREFIX = ~/riscv/bin/
DEFINE UNIX_IASL_BIN = ENV(IASL_PREFIX)iasl
DEFINE WIN_ASL_BIN_DIR = C:\ASL
@@ -4468,6 +4470,19 @@ DEFINE GCC53RISCV_RISCV64_DLINK_FLAGS = DEF(GCC53RISCV_RISCV32_RISCV64_DLI
DEFINE GCC53RISCV_RISCV64_DLINK2_FLAGS = DEF(GCC49_X64_DLINK2_FLAGS)
DEFINE GCC53RISCV_ASM_FLAGS = DEF(GCC49_ASM_FLAGS)
+DEFINE GCC711RISCV_RISCV32_ARCH = rv32imafd
+DEFINE GCC711RISCV_RISCV64_ARCH = rv64imafd
+DEFINE GCC711RISCV_CC_FLAGS_WARNING_DISABLE = -Wno-tautological-compare -Wno-pointer-compare
+DEFINE GCC711RISCV_RISCV32_CC_FLAGS = DEF(GCC44_ALL_CC_FLAGS) DEF(GCC711RISCV_CC_FLAGS_WARNING_DISABLE) -march=DEF(GCC711RISCV_RISCV32_ARCH) -malign-double -fno-stack-protector -D EFI32 -fno-asynchronous-unwind-tables -Wno-address -Wno-unused-but-set-variable -fpack-struct=8
+DEFINE GCC711RISCV_RISCV64_CC_FLAGS = DEF(GCC44_ALL_CC_FLAGS) DEF(GCC711RISCV_CC_FLAGS_WARNING_DISABLE) -march=DEF(GCC711RISCV_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fno-asynchronous-unwind-tables -Wno-unused-but-set-variable -fpack-struct=8
+DEFINE GCC711RISCV_RISCV32_RISCV64_DLINK_COMMON = -nostdlib -n -q --gc-sections -z common-page-size=0x40
+DEFINE GCC711RISCV_RISCV32_RISCV64_ASLDLINK_FLAGS = DEF(GCC53RISCV_RISCV32_RISCV64_DLINK_COMMON) --entry ReferenceAcpiTable -u ReferenceAcpiTable
+DEFINE GCC711RISCV_RISCV32_RISCV64_DLINK_FLAGS = DEF(GCC53RISCV_RISCV32_RISCV64_DLINK_COMMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
+DEFINE GCC711RISCV_RISCV32_DLINK2_FLAGS = DEF(GCC49_IA32_DLINK2_FLAGS)
+DEFINE GCC711RISCV_RISCV64_DLINK_FLAGS = DEF(GCC53RISCV_RISCV32_RISCV64_DLINK_FLAGS) -melf64lriscv --oformat=elf64-littleriscv --no-relax
+DEFINE GCC711RISCV_RISCV64_DLINK2_FLAGS = DEF(GCC49_X64_DLINK2_FLAGS)
+DEFINE GCC711RISCV_ASM_FLAGS = DEF(GCC49_ASM_FLAGS)
+
####################################################################################
#
# Unix GCC And Intel Linux ACPI Compiler
@@ -5269,6 +5284,74 @@ RELEASE_GCC49_AARCH64_DLINK_FLAGS = DEF(GCC49_AARCH64_DLINK_FLAGS)
####################################################################################
#
+# GCC 7.1.1 RISC-V This configuration is used to compile under Linux to produce
+# PE/COFF binaries using GCC 7.1.1.
+#
+####################################################################################
+
+*_GCC711RISCV_*_*_FAMILY = GCC
+
+*_GCC711RISCV_*_MAKE_PATH = DEF(GCC49_IA32_PREFIX)make
+*_GCC711RISCV_*_PP_FLAGS = DEF(GCC_PP_FLAGS)
+*_GCC711RISCV_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS)
+*_GCC711RISCV_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_GCC711RISCV_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS)
+*_GCC711RISCV_*_APP_FLAGS =
+*_GCC711RISCV_*_ASL_FLAGS = DEF(IASL_FLAGS)
+*_GCC711RISCV_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
+
+##################
+# GCC711RISCV RISCV32 definitions
+##################
+
+*_GCC711RISCV_RISCV32_OBJCOPY_PATH = ENV(GCC711RISCV_RISCV32_PREFIX)riscv64-unknown-elf-objcopy
+*_GCC711RISCV_RISCV32_SLINK_PATH = ENV(GCC711RISCV_RISCV32_PREFIX)riscv64-unknown-elf-gcc-ar
+*_GCC711RISCV_RISCV32_DLINK_PATH = ENV(GCC711RISCV_RISCV32_PREFIX)riscv64-unknown-elf-ld
+*_GCC711RISCV_RISCV32_ASLDLINK_PATH = ENV(GCC711RISCV_RISCV32_PREFIX)riscv64-unknown-elf-ld
+*_GCC711RISCV_RISCV32_ASM_PATH = ENV(GCC711RISCV_RISCV32_PREFIX)riscv64-unknown-elf-gcc
+*_GCC711RISCV_RISCV32_PP_PATH = ENV(GCC711RISCV_RISCV32_PREFIX)riscv64-unknown-elf-gcc
+*_GCC711RISCV_RISCV32_VFRPP_PATH = ENV(GCC711RISCV_RISCV32_PREFIX)riscv64-unknown-elf-gcc
+*_GCC711RISCV_RISCV32_ASLCC_PATH = ENV(GCC711RISCV_RISCV32_PREFIX)riscv64-unknown-elf-gcc
+*_GCC711RISCV_RISCV32_ASLPP_PATH = ENV(GCC711RISCV_RISCV32_PREFIX)riscv64-unknown-elf-gcc
+*_GCC711RISCV_RISCV32_RC_PATH = ENV(GCC711RISCV_RISCV32_PREFIX)riscv64-unknown-elf-objcopy
+
+*_GCC711RISCV_RISCV32_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m32
+*_GCC711RISCV_RISCV32_ASLDLINK_FLAGS = DEF(GCC711RISCV_RISCV32_RISCV64_ASLDLINK_FLAGS) -m elf_i386
+*_GCC711RISCV_RISCV32_ASM_FLAGS = DEF(GCC711RISCV_ASM_FLAGS) -m32 -march=i386
+*_GCC711RISCV_RISCV32_CC_FLAGS = DEF(GCC711RISCV_RISCV32_CC_FLAGS) -Os
+*_GCC711RISCV_RISCV32_DLINK_FLAGS = DEF(GCC711RISCV_RISCV32_RISCV64_DLINK_FLAGS) -m elf_i386 --oformat=elf32-i386
+*_GCC711RISCV_RISCV32_DLINK2_FLAGS = DEF(GCC711RISCV_RISCV32_DLINK2_FLAGS)
+*_GCC711RISCV_RISCV32_RC_FLAGS = DEF(GCC_IA32_RC_FLAGS)
+*_GCC711RISCV_RISCV32_OBJCOPY_FLAGS =
+*_GCC711RISCV_RISCV32_NASM_FLAGS = -f elf32
+
+##################
+# GCC711RISCV RISCV64 definitions
+##################
+*_GCC711RISCV_RISCV64_OBJCOPY_PATH = ENV(GCC711RISCV_RISCV64_PREFIX)riscv64-unknown-elf-objcopy
+*_GCC711RISCV_RISCV64_CC_PATH = ENV(GCC711RISCV_RISCV64_PREFIX)riscv64-unknown-elf-gcc
+*_GCC711RISCV_RISCV64_SLINK_PATH = ENV(GCC711RISCV_RISCV64_PREFIX)riscv64-unknown-elf-gcc-ar
+*_GCC711RISCV_RISCV64_DLINK_PATH = ENV(GCC711RISCV_RISCV64_PREFIX)riscv64-unknown-elf-ld
+*_GCC711RISCV_RISCV64_ASLDLINK_PATH = ENV(GCC711RISCV_RISCV64_PREFIX)riscv64-unknown-elf-ld
+*_GCC711RISCV_RISCV64_ASM_PATH = ENV(GCC711RISCV_RISCV64_PREFIX)riscv64-unknown-elf-gcc
+*_GCC711RISCV_RISCV64_PP_PATH = ENV(GCC711RISCV_RISCV64_PREFIX)riscv64-unknown-elf-gcc
+*_GCC711RISCV_RISCV64_VFRPP_PATH = ENV(GCC711RISCV_RISCV64_PREFIX)riscv64-unknown-elf-gcc
+*_GCC711RISCV_RISCV64_ASLCC_PATH = ENV(GCC711RISCV_RISCV64_PREFIX)riscv64-unknown-elf-gcc
+*_GCC711RISCV_RISCV64_ASLPP_PATH = ENV(GCC711RISCV_RISCV64_PREFIX)riscv64-unknown-elf-gcc
+*_GCC711RISCV_RISCV64_RC_PATH = ENV(GCC711RISCV_RISCV64_PREFIX)riscv64-unknown-elf-objcopy
+
+*_GCC711RISCV_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m64
+*_GCC711RISCV_RISCV64_ASLDLINK_FLAGS = DEF(GCC711RISCV_RISCV32_RISCV64_ASLDLINK_FLAGS) -m elf_x86_64
+*_GCC711RISCV_RISCV64_ASM_FLAGS = DEF(GCC711RISCV_ASM_FLAGS)
+*_GCC711RISCV_RISCV64_CC_FLAGS = DEF(GCC711RISCV_RISCV64_CC_FLAGS) -save-temps
+*_GCC711RISCV_RISCV64_DLINK_FLAGS = DEF(GCC711RISCV_RISCV64_DLINK_FLAGS)
+*_GCC711RISCV_RISCV64_DLINK2_FLAGS = DEF(GCC711RISCV_RISCV64_DLINK2_FLAGS)
+*_GCC711RISCV_RISCV64_RC_FLAGS = DEF(GCC_IA32_RC_FLAGS)
+*_GCC711RISCV_RISCV64_OBJCOPY_FLAGS =
+*_GCC711RISCV_RISCV64_NASM_FLAGS = -f elf64
+
+####################################################################################
+#
# CLANG35 - This configuration is used to compile under Linux to produce
# PE/COFF binaries using the clang compiler and assembler (v3.5 and up)
# and GNU linker
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [staging/branch RISC-V PATCH 3/4] BaseTools: Add more RISC-V relocation types.
2017-07-04 5:29 [staging/branch RISC-V PATCH 0/4] RISC-V edk2 port GCC 7.1.1 Abner Chang
2017-07-04 5:29 ` [staging/branch RISC-V PATCH 1/4] RiscVPkg/Sec: Use MRET in machine trap handler Abner Chang
2017-07-04 5:29 ` [staging/branch RISC-V PATCH 2/4] BaseTools: Support RISC-V GCC 7.1.1 Abner Chang
@ 2017-07-04 5:29 ` Abner Chang
2017-07-04 5:29 ` [staging/branch RISC-V PATCH 4/4] RiscVVirtPkg: Update README file Abner Chang
3 siblings, 0 replies; 5+ messages in thread
From: Abner Chang @ 2017-07-04 5:29 UTC (permalink / raw)
To: edk2-devel
Add more RISC-V relocation types to prevent from errors happen
when build RISC-V edk2 port by RISC-V gcc 7.1.1.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
BaseTools/Source/C/GenFw/Elf64Convert.c | 18 +++++++++++++++++-
BaseTools/Source/C/GenFw/elf_common.h | 10 +++++++++-
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 9deb846..4857485 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -3,7 +3,7 @@ Elf64 convert solution
Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
-Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2016-2017, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License which accompanies this
@@ -953,6 +953,14 @@ WriteSections64 (
case R_RISCV_GPREL_I:
case R_RISCV_GPREL_S:
case R_RISCV_CALL:
+ case R_RISCV_RVC_BRANCH:
+ case R_RISCV_RVC_JUMP:
+ case R_RISCV_RELAX:
+ case R_RISCV_SUB6:
+ case R_RISCV_SET6:
+ case R_RISCV_SET8:
+ case R_RISCV_SET16:
+ case R_RISCV_SET32:
break;
default:
@@ -1129,6 +1137,14 @@ WriteRelocations64 (
case R_RISCV_GPREL_I:
case R_RISCV_GPREL_S:
case R_RISCV_CALL:
+ case R_RISCV_RVC_BRANCH:
+ case R_RISCV_RVC_JUMP:
+ case R_RISCV_RELAX:
+ case R_RISCV_SUB6:
+ case R_RISCV_SET6:
+ case R_RISCV_SET8:
+ case R_RISCV_SET16:
+ case R_RISCV_SET32:
break;
default:
diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/GenFw/elf_common.h
index 0ff9720..65ec5f7 100644
--- a/BaseTools/Source/C/GenFw/elf_common.h
+++ b/BaseTools/Source/C/GenFw/elf_common.h
@@ -3,7 +3,7 @@ Ported ELF include files from FreeBSD
Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
-Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2016-2017, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -1109,4 +1109,12 @@ typedef struct {
#define R_RISCV_RVC_LUI 46
#define R_RISCV_GPREL_I 47
#define R_RISCV_GPREL_S 48
+#define R_RISCV_TPREL_I 49
+#define R_RISCV_TPREL_S 50
+#define R_RISCV_RELAX 51
+#define R_RISCV_SUB6 52
+#define R_RISCV_SET6 53
+#define R_RISCV_SET8 54
+#define R_RISCV_SET16 55
+#define R_RISCV_SET32 56
#endif /* !_SYS_ELF_COMMON_H_ */
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* [staging/branch RISC-V PATCH 4/4] RiscVVirtPkg: Update README file
2017-07-04 5:29 [staging/branch RISC-V PATCH 0/4] RISC-V edk2 port GCC 7.1.1 Abner Chang
` (2 preceding siblings ...)
2017-07-04 5:29 ` [staging/branch RISC-V PATCH 3/4] BaseTools: Add more RISC-V relocation types Abner Chang
@ 2017-07-04 5:29 ` Abner Chang
3 siblings, 0 replies; 5+ messages in thread
From: Abner Chang @ 2017-07-04 5:29 UTC (permalink / raw)
To: edk2-devel
Update README for supporting RISC-V gcc 7.1.1.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVVirtPkg/README | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/RiscVVirtPkg/README b/RiscVVirtPkg/README
index 64611ad..ff48f62 100644
--- a/RiscVVirtPkg/README
+++ b/RiscVVirtPkg/README
@@ -1,7 +1,7 @@
## @file
# Readme of how to build and launch RiscVVirtPkg on QEMU.
#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2016-2017, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -40,19 +40,23 @@ Current capabilities:
=== Get source code ===
* QEMU RISC-V PC/AT port.
- git clone https://github.com/AbnerChang/RiscVQemuPcat.git
+ git clone https://github.com/AbnerChang/RiscVQemuPcat.git (Latest commit SHA 9992f910 07/03/2017)
-* RISC-V tools
- $git clone https://github.com/riscv/riscv-tools.git (Lastest commit 419f1b5 2016/4/1)
+* RISC-V tools (RISC-V GCC 7.1.1)
+ $git clone https://github.com/riscv/riscv-tools.git (Lastest commit SHA 7cd1d105 06/22/2017)
* EDK2 open source
=== Build RISC-V tool chain ===
Before you build RISC-V tool chain, you need below packages.
-*sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc
+*sudo apt-get install autoconf automake autotools-dev curl device-tree-compiler libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev
*Change directory to riscv-tools
git submodule update --init --recursive
export RISCV=~/riscv
+*In build.sh, add build option "--with-arch=rv64g" to "build_project" as below,
+build_project riscv-gnu-toolchain --prefix=$RISCV --with-arch=rv64g
+This builds RISC-V tool chain to use RISC-V "G" varient.
+*Build RISC-V tool chain
./build.sh
The binaries needed for building EDK2 open source to RISC-V ISA are built in to ~/riscv
@@ -80,7 +84,7 @@ Before you build QEMU RISC-V EDK2, you need belwo package.
*Conf/target.txt
ACTIVE_PLATFORM = RiscVVirtPkg/RiscVVirt64.dsc
TARGET_ARCH = RISCV64
-TOOL_CHAIN_TAG = GCC53RISCV
+TOOL_CHAIN_TAG = GCC711RISCV
*$export PATH=$PATH:~/riscv/bin
*$make -C BaseTools
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread