From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-x229.google.com (mail-lf0-x229.google.com [IPv6:2a00:1450:4010:c07::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9946420945600 for ; Tue, 4 Jul 2017 06:22:50 -0700 (PDT) Received: by mail-lf0-x229.google.com with SMTP id z78so77470280lff.0 for ; Tue, 04 Jul 2017 06:24:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E3JPLUrU5nb2c61DK6Ki6xB4MrtRpe9Y6xmDSdN1tuw=; b=sTJmW1aMZyalCYwR4VdlShlMfZp5FqwA9ZScmX2RUIz3NYtd187A1CPuUQkTl9Ltq6 a88sDgyLu5iKRRC4ACbzprr80jcfwNPi80GKcEMlF7XsnCIq9HclK7Cvw1SJYvX+B7h1 ku1N1Qh9fSw/taWQakuFEc1z+k3wYCHXl8NEihycFq1aXKAfG+e2X8IEfZcHdF6um7Sl Sv5k8s4mIIC+FpJdMGn+vXqQwxQmowxvlnngTepDL9D8gNMULh2L9arEJBSJmBzdbbLw nh5SnCRPz5yMU+ckaJntjP77LdkT/HBEtMQVlPKowrLNTq8vTTv0E2TiGcNikyDYWWss j3pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=E3JPLUrU5nb2c61DK6Ki6xB4MrtRpe9Y6xmDSdN1tuw=; b=I7JbJLAQhO7r5m+cMwmZtSrOhA9yEVVWn6KOyQ053Dv3p7O3sP9WHi0sr4rruLWYbP qbCFdBSt6sa1qy62leAAZ6mNzK33lpdVfERURLpW5OWX0bPrCVmEpgPXJP8bQx4J0mHo kc1o4Z0TEVIe/b7rI0LCnYNPEgAZojKBngZy/j4tb0dsStB+dix+Nk60FxHe+c21guxH k4RnsMSZ8Sw+SGnpRNuKH1dRHrIWVis9yycSZo7plFqDz2uklQXKN6pKizx56P/5XJ39 FkokWYzZBjb0dqWpYXQPK3UWFGU2UrVhZFPF9cp3n0MMkjBT/xQp2RGVUVh0Wrf0Y1cA 8dQg== X-Gm-Message-State: AKS2vOzXCs3Od6h9CQUWTD3F6hUQERLsPi+C4h51/yHyJJkqoBn733JX PwDshI1wi+WSSHjOS+Rjsw== X-Received: by 10.25.74.88 with SMTP id x85mr11360159lfa.31.1499174666443; Tue, 04 Jul 2017 06:24:26 -0700 (PDT) Received: from mw-mint.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:25 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jinghua@marvell.com Date: Tue, 4 Jul 2017 15:24:04 +0200 Message-Id: <1499174653-330-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH 01/10] Platform/Marvell: ComPhyLib: Cleanup and fix SerDes lanes assignment X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jul 2017 13:22:51 -0000 Hitherto settings of ComPhy lanes' options were not on par with real hardware capabilities. This patch introduces following fixes to the lanes options: * Remove XAUI, because it's not supported; * Correct opiton for Lane1 is SATA0; * Remove KR from Lane3; * KR on Lane4 mux selector should be 0x2; * Align SGMII numbering according to the specification. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 30 ++++++++++-------------- 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c index c71ddb6..6214bed 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -49,32 +49,26 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; * and " PIPE Selectors". * PIPE selector include USB and PCIe options. * PHY selector include the Ethernet and SATA options, every Ethernet option - * has different options, for example: serdes Lane2 had option Eth_port_0 - * that include (SGMII0, XAUI0, RXAUI0, KR) + * has different options, for example: serdes Lane2 have option Eth_port_0 + * that include (SGMII0, RXAUI0, KR) */ COMPHY_MUX_DATA Cp110ComPhyMuxData[] = { /* Lane 0 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, - {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, {PHY_TYPE_SATA1, 0x4}}}, /* Lane 1 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, - {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, /* Lane 2 */ - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, - {PHY_TYPE_SATA0, 0x4} } }, + {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, + {PHY_TYPE_KR, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, /* Lane 3 */ - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, - {PHY_TYPE_XAUI1, 0x1}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, + {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII1, 0x2}, + {PHY_TYPE_SATA1, 0x4}}}, /* Lane 4 */ - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, - {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, + {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, {PHY_TYPE_RXAUI0, 0x2}, + {PHY_TYPE_KR, 0x2}, {PHY_TYPE_SGMII1, 0x1}}}, /* Lane 5 */ - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, - {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, {PHY_TYPE_XAUI3, 0x1}, - {PHY_TYPE_SATA1, 0x4} } }, + {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_RXAUI1, 0x2}, + {PHY_TYPE_SATA1, 0x4}}}, }; COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = { -- 2.7.4