From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-x22f.google.com (mail-lf0-x22f.google.com [IPv6:2a00:1450:4010:c07::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 856FC20945601 for ; Tue, 4 Jul 2017 06:22:52 -0700 (PDT) Received: by mail-lf0-x22f.google.com with SMTP id z78so77470821lff.0 for ; Tue, 04 Jul 2017 06:24:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N8XZ2nyVgJ6sXWY4WLvBQb+5tKmhWSQOVv0EohuSgpU=; b=ctCc1EDPkwRclTb+V2kjVOMOyW4mVMDyZT/E0bfPdCYCD/E9AonrFxboRfGKPDX2DU ll3wq/i4/5rHWjRBlrz68mq1UfxUXilq21cmMfAIG6GJ6+adSOIwEC/z3HZrv/n5DX3R 9E3lA6p+i8kfkoeHE8Lsra/AsxY48fQSeZaA9yC0lMxHV57i9hRX0H3hoBEBcZn53RJ5 U3vy1WgsuitQLMZg67pbwj2C7vv+XzN25xAesoEb2DCIadH/rRR1HvGD94xeyrjOhHjn EvYRD5DK/15mbRC5ghSi13CUjFG7C2YSinxpQnv/B7MUqxBLxKLCG4gF8t3OaGrQwf9o sSjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N8XZ2nyVgJ6sXWY4WLvBQb+5tKmhWSQOVv0EohuSgpU=; b=RV8U4DqA4RqL5wx4wj9JvcZpoJ9WZoktrZuuOhwsABZv4RfGKtnRgyDPK0bno0V/tk BelVN2o29GsERRtsR3tcuuQnIX4CDgbItDsKEn5lLzSIvS65QpolZZGp+hXGcWZr0c10 7MwcSr9H0WnjVW2KobfIJTOmk8TG7P0xsgEWewOD7mavnPnFW6NIqk+tEQtcINR7cUmK r8xeViLAnzz+oybDWi52/Ho5sUjhIs5B+/I/RDkTmA82/S97tO2qQyxYhyrpVGUfN96e /Uhgdi5CRVvtIRXMmbHAU/SjeRml/vwrAh2hEFhMJjShHzPWfRLJH5/s18qGWfDdMtnT ccOQ== X-Gm-Message-State: AKS2vOxKrWfPKF2f4MKG9EKP8X6LC+rhwuj5PLSxSCeDlgKzMtS6K7ME V70VYPW8B+DycjgsqmBavA== X-Received: by 10.25.92.18 with SMTP id q18mr11277651lfb.13.1499174668067; Tue, 04 Jul 2017 06:24:28 -0700 (PDT) Received: from mw-mint.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:26 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jinghua@marvell.com Date: Tue, 4 Jul 2017 15:24:05 +0200 Message-Id: <1499174653-330-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH 02/10] Platform/Marvell: ComPhyLib: Rename KR to SFI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jul 2017 13:22:53 -0000 The actual SerDes type present by the HW is SFI, whose suppport is added in the following patches. KR mode is its subset of the SFI and it will be enabled in future. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 6 +++--- Platform/Marvell/Library/ComPhyLib/ComPhyLib.c | 2 +- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c index 6214bed..cee7519 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -50,7 +50,7 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; * PIPE selector include USB and PCIe options. * PHY selector include the Ethernet and SATA options, every Ethernet option * has different options, for example: serdes Lane2 have option Eth_port_0 - * that include (SGMII0, RXAUI0, KR) + * that include (SGMII0, RXAUI0, SFI) */ COMPHY_MUX_DATA Cp110ComPhyMuxData[] = { /* Lane 0 */ @@ -59,13 +59,13 @@ COMPHY_MUX_DATA Cp110ComPhyMuxData[] = { {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, /* Lane 2 */ {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, - {PHY_TYPE_KR, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, + {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4}}}, /* Lane 3 */ {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4}}}, /* Lane 4 */ {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, {PHY_TYPE_RXAUI0, 0x2}, - {PHY_TYPE_KR, 0x2}, {PHY_TYPE_SGMII1, 0x1}}}, + {PHY_TYPE_SFI, 0x2}, {PHY_TYPE_SGMII1, 0x1}}}, /* Lane 5 */ {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4}}}, diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c index 9efefb2..88680fc 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -39,7 +39,7 @@ CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"SGMII0", L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", L"XAUI0", L"XAUI1", L"XAUI2", - L"XAUI3", L"RXAUI0", L"RXAUI1", L"KR"}; + L"XAUI3", L"RXAUI0", L"RXAUI1", L"SFI"}; CHAR16 * SpeedStringTable [] = {L"-", L"1.25 Gbps", L"1.5 Gbps", L"2.5 Gbps", L"3.0 Gbps", L"3.125 Gbps", L"5 Gbps", diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h index 945f266..24839b2 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -109,7 +109,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define PHY_TYPE_XAUI3 20 #define PHY_TYPE_RXAUI0 21 #define PHY_TYPE_RXAUI1 22 -#define PHY_TYPE_KR 23 +#define PHY_TYPE_SFI 23 #define PHY_TYPE_MAX 24 #define PHY_TYPE_INVALID 0xff -- 2.7.4