From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-x235.google.com (mail-lf0-x235.google.com [IPv6:2a00:1450:4010:c07::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3EC7120945610 for ; Tue, 4 Jul 2017 06:22:56 -0700 (PDT) Received: by mail-lf0-x235.google.com with SMTP id t72so9319459lff.1 for ; Tue, 04 Jul 2017 06:24:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cslcrao36bTg265AcXQRtPUpstwBFiBZLBnPO4t+spQ=; b=0BNVclGevGgHdwn1Yrn3ie2fJEhZwXVkcAU5MTd2tG9CtBdVAAaKLd9u6n3Ctp8buH wDa4ZkC+Il4bYIxmkhb+v+LafqrlPrDO8nUpm3FJiq7Nv5LQWCd6KJeaOsFO/2i4BDqI l/7bHwoiqnSfgfLSHFNN4RP5QL2ct92y07TSniV2NBUtQdQx+wjt2x8HMRYCsNAE7ZSe mQQrw64YmkAF+zXsm9J80D/U6WMgIEYnrbTLKpJHteQluvL8Z6CNbv4CtTHhgMzgzLxr w+muSC0CBhG3dySGGHE+JlNwdGIRvFhtzmDn+vnygPU+WenOJk2uINtcn+pwRhCmVTv2 ZWqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cslcrao36bTg265AcXQRtPUpstwBFiBZLBnPO4t+spQ=; b=Gnw3ldC6UvKinPzGfHXzEAPcEiV2WGPJa3Sqk9Yge5uBmYfT7fB4cqg8ngFYtEGs22 mcgt30E/flYPHR1yXGeKGH9Bw2MVteuQBTPoCFG9tFpxMSEm9wFYY/1t9MUzKiedF0G2 7IAfEIzjqPnkIOzJ6lxn6tAW8erlrIG9w4cWoaDKatxBYHBoO/FB6LIT+ejGGwuVsaxZ whEHn9hj3UEknmL03FRTE85i6S+IN0GB8+9p0yYJgm55z4z7dEJIbDR6k432RFiYGaT5 TweF5H4vTIo5BEbMQfNHvymBkDunR7DLH2/D5XEMrYhvafPMfKXUcNzl1SorGec6v6g2 pFhQ== X-Gm-Message-State: AKS2vOyG7MZM4QOL3QHXb8yIo66s0F+gTXgYv2/HEvNW93ypbfh1nrgn 0Z5SBSGydArj3UKYmhlPTQ== X-Received: by 10.46.77.197 with SMTP id c66mr11719126ljd.71.1499174672009; Tue, 04 Jul 2017 06:24:32 -0700 (PDT) Received: from mw-mint.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id c185sm4980970lfc.43.2017.07.04.06.24.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 06:24:31 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jinghua@marvell.com Date: Tue, 4 Jul 2017 15:24:08 +0200 Message-Id: <1499174653-330-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499174653-330-1-git-send-email-mw@semihalf.com> References: <1499174653-330-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH 05/10] Platform/Marvell: ComPhyLib: Configure analog parameters for SATA X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jul 2017 13:22:57 -0000 This patch adds analog parameters configuration for SATA with the values defined during electrical tests of the interface. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 207 +++++++++++++++++++++-- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 148 +++++++++++++--- 2 files changed, 321 insertions(+), 34 deletions(-) diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c index ee3ce99..ea9525a 100755 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -608,20 +608,203 @@ ComPhySataPhyConfiguration ( STATIC VOID ComPhySataSetAnalogParameters ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr + IN EFI_PHYSICAL_ADDRESS HpipeAddr, + IN EFI_PHYSICAL_ADDRESS SdIpAddr ) { + UINT32 Mask, Data; + + /* Hpipe Generation 1 settings 1 */ + Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK | + HPIPE_GX_SET1_RX_SELMUPP_MASK | + HPIPE_GX_SET1_RX_SELMUFI_MASK | + HPIPE_GX_SET1_RX_SELMUFF_MASK | + HPIPE_GX_SET1_RX_DIGCK_DIV_MASK; + Data = (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) | + (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) | + (0x1 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET1_REG, ~Mask, Data); + + /* Hpipe Generation 1 settings 3 */ + Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK | + HPIPE_GX_SET3_FFE_RES_SEL_MASK | + HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK | + HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK | + HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK; + Data = 0xf | + (0x2 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) | + (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) | + (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) | + (0x1 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET3_REG, ~Mask, Data); + + /* Hpipe Generation 2 settings 1 */ + Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK | + HPIPE_GX_SET1_RX_SELMUPP_MASK | + HPIPE_GX_SET1_RX_SELMUFI_MASK | + HPIPE_GX_SET1_RX_SELMUFF_MASK | + HPIPE_GX_SET1_RX_DIGCK_DIV_MASK; + Data = (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) | + (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) | + (0x1 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G2_SET1_REG, ~Mask, Data); + + /* Hpipe Generation 3 settings 1 */ + Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK | + HPIPE_GX_SET1_RX_SELMUPP_MASK | + HPIPE_GX_SET1_RX_SELMUFI_MASK | + HPIPE_GX_SET1_RX_SELMUFF_MASK | + HPIPE_GX_SET1_RX_DFE_EN_MASK | + HPIPE_GX_SET1_RX_DIGCK_DIV_MASK | + HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK; + Data = 0x2 | + (0x2 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) | + (0x3 << HPIPE_GX_SET1_RX_SELMUFI_OFFSET) | + (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) | + (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET) | + (0x2 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET1_REG, ~Mask, Data); + + /* DTL Control */ + Mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK | + HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK | + HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK | + HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK | + HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK | + HPIPE_PWR_CTR_DTL_CLK_MODE_MASK | + HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; + Data = 0x1 | + (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) | + (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) | + (0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) | + (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) | + (0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) | + (0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, ~Mask, Data); + + /* Trigger sampler enable pulse (by toggling the bit) */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_SAMPLER_MASK, + 0x1 << HPIPE_SAMPLER_OFFSET + ); + MmioAnd32 ( + HpipeAddr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, + ~HPIPE_SAMPLER_MASK + ); + + /* VDD Calibration Control 3 */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_VDD_CAL_CTRL_REG, + ~HPIPE_EXT_SELLV_RXSAMPL_MASK, + 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET + ); + + /* DFE Resolution Control */ + MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK); + + /* DFE F3-F5 Coefficient Control */ + MmioAnd32 ( + HpipeAddr + HPIPE_DFE_F3_F5_REG, + ~(HPIPE_DFE_F3_F5_DFE_EN_MASK | HPIPE_DFE_F3_F5_DFE_CTRL_MASK) + ); + + /* Hpipe Generation 3 settings 3 */ + Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK | + HPIPE_GX_SET3_FFE_RES_SEL_MASK | + HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK | + HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK | + HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK; + Data = 0xf | + (0x4 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) | + (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) | + (0x1 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) | + (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET3_REG, ~Mask, Data); + + /* Hpipe Generation 3 settings 4 */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_G3_SET4_REG, + ~HPIPE_GX_SET4_DFE_RES_MASK, + 0x2 << HPIPE_GX_SET4_DFE_RES_OFFSET + ); + + /* Offset Phase Control - force offset and toggle 'valid' bit */ + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PHASE_CONTROL_REG, + ~(HPIPE_OS_PH_OFFSET_MASK | HPIPE_OS_PH_OFFSET_FORCE_MASK), + 0x5c | (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) + ); + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PHASE_CONTROL_REG, + ~HPIPE_OS_PH_VALID_MASK, + 0x1 << HPIPE_OS_PH_VALID_OFFSET + ); + MmioAnd32 ( + HpipeAddr + HPIPE_PHASE_CONTROL_REG, + ~HPIPE_OS_PH_VALID_MASK + ); + + /* Set G1 TX amplitude and TX post emphasis value */ + Mask = HPIPE_GX_SET0_TX_AMP_MASK | + HPIPE_GX_SET0_TX_AMP_ADJ_MASK | + HPIPE_GX_SET0_TX_EMPH1_MASK | + HPIPE_GX_SET0_TX_EMPH1_EN_MASK; + Data = (0x8 << HPIPE_GX_SET0_TX_AMP_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G1_SET0_REG, ~Mask, Data); + + /* Set G2 TX amplitude and TX post emphasis value */ + Mask = HPIPE_GX_SET0_TX_AMP_MASK | + HPIPE_GX_SET0_TX_AMP_ADJ_MASK | + HPIPE_GX_SET0_TX_EMPH1_MASK | + HPIPE_GX_SET0_TX_EMPH1_EN_MASK; + Data = (0xa << HPIPE_GX_SET0_TX_AMP_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) | + (0x2 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G2_SET0_REG, ~Mask, Data); + + /* Set G3 TX amplitude and TX post emphasis value */ + Mask = HPIPE_GX_SET0_TX_AMP_MASK | + HPIPE_GX_SET0_TX_AMP_ADJ_MASK | + HPIPE_GX_SET0_TX_EMPH1_MASK | + HPIPE_GX_SET0_TX_EMPH1_EN_MASK | + HPIPE_GX_SET0_TX_SLEW_RATE_SEL_MASK | + HPIPE_GX_SET0_TX_SLEW_CTRL_EN_MASK; + Data = (0xe << HPIPE_GX_SET0_TX_AMP_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) | + (0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET) | + (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET) | + (0x4 << HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET); + MmioAndThenOr32 (HpipeAddr + HPIPE_G3_SET0_REG, ~Mask, Data); + + /* SERDES External Configuration 2 register - enable spread spectrum clock */ + MmioOr32 (SdIpAddr + SD_EXTERNAL_CONFIG2_REG, SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK); + /* DFE reset sequence */ - RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, - 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); - RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, - 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PWR_CTR_REG, + ~HPIPE_PWR_CTR_RST_DFE_MASK, + 0x1 + ); + MmioAnd32 ( + HpipeAddr + HPIPE_PWR_CTR_REG, + ~HPIPE_PWR_CTR_RST_DFE_MASK + ); /* SW reset for interupt logic */ - RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, - 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); - RegSet (HpipeAddr + HPIPE_PWR_CTR_REG, - 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); + MmioAndThenOr32 ( + HpipeAddr + HPIPE_PWR_CTR_REG, + ~HPIPE_PWR_CTR_SFT_RST_MASK, + 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET + ); + MmioAnd32 ( + HpipeAddr + HPIPE_PWR_CTR_REG, + ~HPIPE_PWR_CTR_SFT_RST_MASK + ); } STATIC @@ -738,7 +921,7 @@ ComPhySataPowerUp ( DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n")); - ComPhySataSetAnalogParameters (HpipeAddr); + ComPhySataSetAnalogParameters (HpipeAddr, SdIpAddr); DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); @@ -930,8 +1113,8 @@ ComPhySgmiiPowerUp ( /* Set analog paramters from ETP(HW) - for now use the default data */ DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n")); - RegSet (HpipeAddr + HPIPE_G1_SET_0_REG, - 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); + RegSet (HpipeAddr + HPIPE_G1_SET0_REG, + 0x1 << HPIPE_GX_SET0_TX_EMPH1_OFFSET, HPIPE_GX_SET0_TX_EMPH1_MASK); DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - Power Up PLL,Tx,Rx\n")); diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h index 24839b2..8418315 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -143,6 +143,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) +#define SD_EXTERNAL_CONFIG2_REG 0x8 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) #define SD_EXTERNAL_STATUS0_REG 0x18 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 @@ -176,19 +181,39 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) -#define HPIPE_G1_SET_0_REG 0x034 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) - -#define HPIPE_G1_SET_1_REG 0x038 -#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 -#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 -#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) -#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 -#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) - -#define HPIPE_G2_SETTINGS_1_REG 0x040 +#define HPIPE_G1_SET0_REG 0x034 +#define HPIPE_G2_SET0_REG 0x03c +#define HPIPE_G3_SET0_REG 0x044 +#define HPIPE_GX_SET0_TX_AMP_OFFSET 1 +#define HPIPE_GX_SET0_TX_AMP_MASK (0x1f << HPIPE_GX_SET0_TX_AMP_OFFSET) +#define HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET 6 +#define HPIPE_GX_SET0_TX_AMP_ADJ_MASK (0x1 << HPIPE_GX_SET0_TX_AMP_ADJ_OFFSET) +#define HPIPE_GX_SET0_TX_EMPH1_OFFSET 7 +#define HPIPE_GX_SET0_TX_EMPH1_MASK (0xf << HPIPE_GX_SET0_TX_EMPH1_OFFSET) +#define HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET 11 +#define HPIPE_GX_SET0_TX_EMPH1_EN_MASK (0x1 << HPIPE_GX_SET0_TX_EMPH1_EN_OFFSET) +#define HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET 12 +#define HPIPE_GX_SET0_TX_SLEW_RATE_SEL_MASK (0x7 << HPIPE_GX_SET0_TX_SLEW_RATE_SEL_OFFSET) +#define HPIPE_GX_SET0_TX_SLEW_CTRL_EN_OFFSET 15 +#define HPIPE_GX_SET0_TX_SLEW_CTRL_EN_MASK (0x1 << HPIPE_GX_SET0_TX_SLEW_CTRL_EN_OFFSET) + +#define HPIPE_G1_SET1_REG 0x038 +#define HPIPE_G2_SET1_REG 0x040 +#define HPIPE_G3_SET1_REG 0x048 +#define HPIPE_GX_SET1_RX_SELMUPI_OFFSET 0 +#define HPIPE_GX_SET1_RX_SELMUPI_MASK (0x7 << HPIPE_GX_SET1_RX_SELMUPI_OFFSET) +#define HPIPE_GX_SET1_RX_SELMUPP_OFFSET 3 +#define HPIPE_GX_SET1_RX_SELMUPP_MASK (0x7 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET) +#define HPIPE_GX_SET1_RX_SELMUFI_OFFSET 6 +#define HPIPE_GX_SET1_RX_SELMUFI_MASK (0x3 << HPIPE_GX_SET1_RX_SELMUFI_OFFSET) +#define HPIPE_GX_SET1_RX_SELMUFF_OFFSET 8 +#define HPIPE_GX_SET1_RX_SELMUFF_MASK (0x3 << HPIPE_GX_SET1_RX_SELMUFF_OFFSET) +#define HPIPE_GX_SET1_RX_DFE_EN_OFFSET 10 +#define HPIPE_GX_SET1_RX_DFE_EN_MASK (0x1 << HPIPE_GX_SET1_RX_DFE_EN_OFFSET) +#define HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET 11 +#define HPIPE_GX_SET1_RX_DIGCK_DIV_MASK (0x3 << HPIPE_GX_SET1_RX_DIGCK_DIV_OFFSET) +#define HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_OFFSET 13 +#define HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_MASK (0x1 << HPIPE_GX_SET1_SAMPLER_INPAIRX2_EN_OFFSET) #define HPIPE_LOOPBACK_REG 0x08c #define HPIPE_LOOPBACK_SEL_OFFSET 1 @@ -210,6 +235,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 +#define HPIPE_VDD_CAL_CTRL_REG 0x114 +#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 +#define HPIPE_EXT_SELLV_RXSAMPL_MASK (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) + +#define HPIPE_VDD_CAL_0_REG 0x108 +#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 +#define HPIPE_CAL_VDD_CONT_MODE_MASK (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) + #define HPIPE_PCIE_REG0 0x120 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 #define HPIPE_PCIE_IDLE_SYNC_MASK (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) @@ -244,11 +277,57 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_PLLINTP_REG1 0x150 -#define HPIPE_PWR_CTR_DTL_REG 0x184 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 0x2 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) - -#define HPIPE_RX_REG3 0x188 +#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C +#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 +#define HPIPE_RX_SAMPLER_OS_GAIN_MASK (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) +#define HPIPE_SAMPLER_OFFSET 12 +#define HPIPE_SAMPLER_MASK (0x1 << HPIPE_SAMPLER_OFFSET) + +#define HPIPE_TX_REG1_REG 0x174 +#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 +#define HPIPE_TX_REG1_TX_EMPH_RES_MASK (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) +#define HPIPE_TX_REG1_SLC_EN_OFFSET 10 +#define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) + +#define HPIPE_PWR_CTR_DTL_REG 0x184 +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 +#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) + +#define HPIPE_PHASE_CONTROL_REG 0x188 +#define HPIPE_OS_PH_OFFSET_OFFSET 0 +#define HPIPE_OS_PH_OFFSET_MASK (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) +#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 +#define HPIPE_OS_PH_OFFSET_FORCE_MASK (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) +#define HPIPE_OS_PH_VALID_OFFSET 8 +#define HPIPE_OS_PH_VALID_MASK (0x1 << HPIPE_OS_PH_VALID_OFFSET) + +#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 +#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 +#define HPIPE_TRAIN_PAT_NUM_MASK (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) + +#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) + +#define HPIPE_DME_REG 0x228 +#define HPIPE_DME_ETHERNET_MODE_OFFSET 7 +#define HPIPE_DME_ETHERNET_MODE_MASK (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) + +#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 +#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 +#define HPIPE_TX_TRAIN_P2P_HOLD_MASK (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) #define HPIPE_TX_TRAIN_CTRL_REG 0x26C #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 @@ -267,10 +346,35 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) -#define HPIPE_G1_SETTINGS_3_REG 0x440 -#define HPIPE_G1_SETTINGS_4_REG 0x444 -#define HPIPE_G2_SETTINGS_3_REG 0x448 -#define HPIPE_G2_SETTINGS_4_REG 0x44C +#define HPIPE_G1_SET3_REG 0x440 +#define HPIPE_G2_SET3_REG 0x448 +#define HPIPE_G3_SET3_REG 0x450 +#define HPIPE_GX_SET3_FFE_CAP_SEL_OFFSET 0 +#define HPIPE_GX_SET3_FFE_CAP_SEL_MASK (0xf << HPIPE_GX_SET3_FFE_CAP_SEL_OFFSET) +#define HPIPE_GX_SET3_FFE_RES_SEL_OFFSET 4 +#define HPIPE_GX_SET3_FFE_RES_SEL_MASK (0x7 << HPIPE_GX_SET3_FFE_RES_SEL_OFFSET) +#define HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET 7 +#define HPIPE_GX_SET3_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_GX_SET3_FFE_SETTING_FORCE_OFFSET) +#define HPIPE_GX_SET3_FBCK_SEL_OFFSET 9 +#define HPIPE_GX_SET3_FBCK_SEL_MASK (0x1 << HPIPE_GX_SET3_FBCK_SEL_OFFSET) +#define HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET 12 +#define HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_GX_SET3_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET 14 +#define HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_GX_SET3_FFE_LOAD_RES_LEVEL_OFFSET) + +#define HPIPE_G1_SET4_REG 0x444 +#define HPIPE_G2_SET4_REG 0x44C +#define HPIPE_G3_SET4_REG 0x454 +#define HPIPE_GX_SET4_DFE_RES_OFFSET 8 +#define HPIPE_GX_SET4_DFE_RES_MASK (0x3 << HPIPE_GX_SET4_DFE_RES_OFFSET) + +#define HPIPE_TX_PRESET_INDEX_REG 0x468 +#define HPIPE_TX_PRESET_INDEX_OFFSET 0 +#define HPIPE_TX_PRESET_INDEX_MASK (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) + +#define HPIPE_DFE_CONTROL_REG 0x470 +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) #define HPIPE_DFE_CTRL_28_REG 0x49C #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 -- 2.7.4