From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-x22a.google.com (mail-pf0-x22a.google.com [IPv6:2607:f8b0:400e:c00::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E5DA9209455F8 for ; Tue, 4 Jul 2017 08:42:16 -0700 (PDT) Received: by mail-pf0-x22a.google.com with SMTP id e7so117053323pfk.0 for ; Tue, 04 Jul 2017 08:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=XXUgTfO0LTcQ8kNH++J1e5/g0Mnb7rVlz0JV/4/pHk0=; b=UUrafvHAxurwuuHntABV1FDkPkP/GwpHha99nUmzkiBR968F7yWhapPP3ETqinI/ak 3uKlM0mgFzCyX6GAJW3VykoZmQbCFKtuPWgtyDai3BRBCZ8ZWyI/OHwZdI+fR8knT3ad 1mJGaPJlrxbhnoTREwCzm1rjs4gluuaahzPQc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=XXUgTfO0LTcQ8kNH++J1e5/g0Mnb7rVlz0JV/4/pHk0=; b=EJiQcG9kxyjK2Ivv+mJwJchV7jLsThjB/ADdRKMC6lWwtpAdiYqoBlMw0d3yiDs2KL 74Bk2rKhl1ky/XHkvVhkEGkg0FEvNIimGGga78fIIW+C4463c8cbFLM42/k+6Cxl4fL1 gA90XMvc3V2qhAFplYWDaVGGzs9JoEH2d7DWWiaHsvBUrK4esHZXztKDtifKXLInJvLy U7J7FJ7OgyOsfJwGoG++ug0P+q4pViqFJQKIq1cROFYnj64NrruSaH3QNSHiSAzhuiPM XmhuT03hlcmc/iJn2rnuc8tHh7xo2Dlmu4R4zkqmLsZHR+aCVvWeYzamFjujDBqoqZYP DPdA== X-Gm-Message-State: AIVw1103XoC8E/IcmLXiXa+O3sRNpJ1o5baUf8I7pgKGiwMXm5uG+goI xNGNFIL8aDDWFw2D X-Received: by 10.84.215.203 with SMTP id g11mr17455164plj.287.1499183034924; Tue, 04 Jul 2017 08:43:54 -0700 (PDT) Received: from localhost.localdomain ([113.53.228.78]) by smtp.gmail.com with ESMTPSA id z70sm32275828pgz.3.2017.07.04.08.43.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Jul 2017 08:43:54 -0700 (PDT) From: Jun Nie To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, edk2-devel@lists.01.org, evan.lloyd@arm.com, Alexei.Fedorov@arm.com Cc: shawn.guo@linaro.org, jason.liu@linaro.org, Jun Nie Date: Tue, 4 Jul 2017 23:43:38 +0800 Message-Id: <1499183018-16297-1-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 Subject: [PATCH v2] ArmPlatformPkg: Support different PL011 reg offset X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jul 2017 15:42:17 -0000 ZTE/SanChip version pl011 has different reg offset and bit offset for some registers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jun Nie --- ArmPlatformPkg/ArmPlatformPkg.dec | 1 + ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf | 1 + ArmPlatformPkg/Include/Drivers/PL011Uart.h | 29 ++++++++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index d756fd2..3dd613c 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -97,6 +97,7 @@ gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020 gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F + gArmPlatformTokenSpaceGuid.PL011UartZxRegOffset|0|UINT8|0 ## PL011 Serial Debug UART gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030 diff --git a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf index 0154f3b..257fbc7 100644 --- a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf +++ b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf @@ -39,3 +39,4 @@ gArmPlatformTokenSpaceGuid.PL011UartInteger gArmPlatformTokenSpaceGuid.PL011UartFractional + gArmPlatformTokenSpaceGuid.PL011UartZxRegOffset diff --git a/ArmPlatformPkg/Include/Drivers/PL011Uart.h b/ArmPlatformPkg/Include/Drivers/PL011Uart.h index d5e88e8..09d548b 100644 --- a/ArmPlatformPkg/Include/Drivers/PL011Uart.h +++ b/ArmPlatformPkg/Include/Drivers/PL011Uart.h @@ -19,6 +19,7 @@ #include // PL011 Registers +#if !FixedPcdGet8 (PL011UartZxRegOffset) #define UARTDR 0x000 #define UARTRSR 0x004 #define UARTECR 0x004 @@ -34,6 +35,22 @@ #define UARTMIS 0x040 #define UARTICR 0x044 #define UARTDMACR 0x048 +#else +#define UARTDR 0x004 +#define UARTRSR 0x010 +#define UARTECR 0x010 +#define UARTFR 0x014 +#define UARTIBRD 0x024 +#define UARTFBRD 0x028 +#define UARTLCR_H 0x030 +#define UARTCR 0x034 +#define UARTIFLS 0x038 +#define UARTIMSC 0x040 +#define UARTRIS 0x044 +#define UARTMIS 0x048 +#define UARTICR 0x04c +#define UARTDMACR 0x050 +#endif #define UARTPID0 0xFE0 #define UARTPID1 0xFE4 @@ -47,6 +64,7 @@ #define UART_STATUS_ERROR_MASK 0x0F // Flag reg bits +#if !FixedPcdGet8 (PL011UartZxRegOffset) #define PL011_UARTFR_RI (1 << 8) // Ring indicator #define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty #define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full @@ -56,6 +74,17 @@ #define PL011_UARTFR_DCD (1 << 2) // Data carrier detect #define PL011_UARTFR_DSR (1 << 1) // Data set ready #define PL011_UARTFR_CTS (1 << 0) // Clear to send +#else +#define PL011_UARTFR_RI (1 << 0) // Ring indicator +#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty +#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full +#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full +#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty +#define PL011_UARTFR_BUSY (1 << 8) // UART busy +#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect +#define PL011_UARTFR_DSR (1 << 3) // Data set ready +#define PL011_UARTFR_CTS (1 << 1) // Clear to send +#endif // Flag reg bits - alternative names #define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE -- 1.9.1