From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D075321CF25DC for ; Mon, 10 Jul 2017 19:17:34 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jul 2017 19:19:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,343,1496127600"; d="scan'208";a="106818900" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga004.jf.intel.com with ESMTP; 10 Jul 2017 19:19:19 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Jeff Fan Date: Tue, 11 Jul 2017 10:19:15 +0800 Message-Id: <1499739556-14440-2-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1499739556-14440-1-git-send-email-eric.dong@intel.com> References: <1499739556-14440-1-git-send-email-eric.dong@intel.com> Subject: [Patch V2 1/2] UefiCpuPkg RegisterCpuFeaturesLib: Add error handling code. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 11 Jul 2017 02:17:35 -0000 Add error handling code when initialize the CPU feature failed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong Cc: Jeff Fan --- .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 47 +++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index 5e11b2b..e91a438 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -235,6 +235,31 @@ SupportedMaskAnd ( } /** + Worker function to clean bit operation on CPU feature supported bits mask buffer. + + @param[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer + @param[in] AndFeatureBitMask The feature bit mask to do XOR operation +**/ +VOID +SupportedMaskCleanBit ( + IN UINT8 *SupportedFeatureMask, + IN UINT8 *AndFeatureBitMask + ) +{ + UINTN Index; + UINTN BitMaskSize; + UINT8 *Data1; + UINT8 *Data2; + + BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport); + Data1 = SupportedFeatureMask; + Data2 = AndFeatureBitMask; + for (Index = 0; Index < BitMaskSize; Index++) { + *(Data1++) &= ~(*(Data2++)); + } +} + +/** Worker function to check if the compared CPU feature set in the CPU feature supported bits mask buffer. @@ -497,12 +522,32 @@ AnalysisProcessorFeatures ( CpuFeatureInOrder = CPU_FEATURE_ENTRY_FROM_LINK (Entry); if (IsBitMaskMatch (CpuFeatureInOrder->FeatureMask, CpuFeaturesData->SettingPcds)) { Status = CpuFeatureInOrder->InitializeFunc (ProcessorNumber, CpuInfo, CpuFeatureInOrder->ConfigData, TRUE); + if (EFI_ERROR (Status)) { + // + // Clean the CpuFeatureInOrder->FeatureMask in setting PCD. + // + SupportedMaskCleanBit (CpuFeaturesData->SettingPcds, CpuFeatureInOrder->FeatureMask); + if (CpuFeatureInOrder->FeatureName != NULL) { + DEBUG ((DEBUG_WARN, "Warning :: Failed to enable Feature Name = %a.\n", CpuFeatureInOrder->FeatureName)); + } else { + DEBUG ((DEBUG_WARN, "Warning :: Failed to enable Feature Mask = ")); + DumpCpuFeatureMask (CpuFeatureInOrder->FeatureMask); + } + } } else { Status = CpuFeatureInOrder->InitializeFunc (ProcessorNumber, CpuInfo, CpuFeatureInOrder->ConfigData, FALSE); + ASSERT_EFI_ERROR (Status); } - ASSERT_EFI_ERROR (Status); Entry = Entry->ForwardLink; } + + // + // Dump PcdCpuFeaturesSetting again because this value maybe updated + // again during initialize the features. + // + DEBUG ((DEBUG_INFO, "Dump final value for PcdCpuFeaturesSetting:\n")); + DumpCpuFeatureMask (CpuFeaturesData->SettingPcds); + // // Dump the RegisterTable // -- 2.7.0.windows.1