From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web08.919.1647050070631942533 for ; Fri, 11 Mar 2022 17:55:27 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=e2w3wLHj; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647050126; x=1678586126; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZYfj9fXhavl8B0wn03+tCb64zKWpNHcL68O6AiciY5U=; b=e2w3wLHja1yVoduDBDGP+XO36SlnCjo6JIdOy+uaNDcGPjPFSvpVcCI+ EYrhrFeKT2rzqgMUyCXNTpaKSpnz8lajmbP3st5Re4u/qE62Ocdl5ezyg J5qURBLN5lKJvpRR7rLsh0siDq3cNIzFx/5rhIbMlM8K39MC5mwDFxHHr k2WkaDy/u/agxuhtsfVHI/+5AUFxF6JUl9zGtsbmmgN0T1DnUR2J3rOkD qzPF2x0cpPl7Bp6f7FT5EZiSyngTTq4ZRGCbHoCjJIDqOwo4Z2r/ZNNlv gQqYyGU2+wfshR1xTBcQGOdDJbzD5pXUSEKW8uZlS5Y0Psnp1fX8OiKvn Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10283"; a="255894469" X-IronPort-AV: E=Sophos;i="5.90,175,1643702400"; d="scan'208";a="255894469" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2022 17:55:26 -0800 X-IronPort-AV: E=Sophos;i="5.90,175,1643702400"; d="scan'208";a="555564680" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.29.254]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2022 17:55:23 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [PATCH V8 19/47] OvmfPkg/PlatformPei: Refactor MiscInitialization Date: Sat, 12 Mar 2022 09:53:44 +0800 Message-Id: <14e29536cd50ddfd9443bcfd70da5c0438ac704f.1647047482.git.min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 In MiscInitialization Microvm looks a little weird. Other platforms call PcdSet16S to set the PcdOvmfHostBridgePciDevId with the value same as PlatformInfoHob->HostBridgeDevId. But Microvm doesn't follow this way. In switch-case 0xffff is Microvm, but set with MICROVM_PSEUDO_DEVICE_ID. So we have to add a new function ( MiscInitializationForMicrovm ) for Microvm and delete the code in MiscInitialization. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu --- OvmfPkg/PlatformPei/Platform.c | 46 ++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 10 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 80eb4cc9adcd..af9e72cd7a98 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -304,6 +304,36 @@ MicrovmInitialization ( *FdtHobData = (UINTN)NewBase; } +VOID +MiscInitializationForMicrovm ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + RETURN_STATUS PcdStatus; + + ASSERT (PlatformInfoHob->HostBridgeDevId == 0xffff); + + DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__)); + // + // Disable A20 Mask + // + IoOr8 (0x92, BIT1); + + // + // Build the CPU HOB with guest RAM size dependent address width and 16-bits + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during + // S3 resume as well, so we build it unconditionally.) + // + BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16); + + MicrovmInitialization (); + PcdStatus = PcdSet16S ( + PcdOvmfHostBridgePciDevId, + MICROVM_PSEUDO_DEVICE_ID + ); + ASSERT_RETURN_ERROR (PcdStatus); +} + VOID MiscInitialization ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob @@ -349,15 +379,6 @@ MiscInitialization ( AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN; break; - case 0xffff: /* microvm */ - DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__)); - MicrovmInitialization (); - PcdStatus = PcdSet16S ( - PcdOvmfHostBridgePciDevId, - MICROVM_PSEUDO_DEVICE_ID - ); - ASSERT_RETURN_ERROR (PcdStatus); - return; case CLOUDHV_DEVICE_ID: DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION__)); PcdStatus = PcdSet16S ( @@ -762,7 +783,12 @@ InitializePlatform ( InstallClearCacheCallback (); AmdSevInitialize (); - MiscInitialization (&mPlatformInfoHob); + if (mPlatformInfoHob.HostBridgeDevId == 0xffff) { + MiscInitializationForMicrovm (&mPlatformInfoHob); + } else { + MiscInitialization (&mPlatformInfoHob); + } + InstallFeatureControlCallback (); return EFI_SUCCESS; -- 2.29.2.windows.2