* [Patch 1/4] UefiCpuPkg: Add PPIN related MSR for Xeon E5.
2017-07-14 2:49 [Patch 0/4] Enable PPIN Cpu feature Eric Dong
@ 2017-07-14 2:49 ` Eric Dong
2017-07-14 2:49 ` [Patch 2/4] UefiCpuPkg RegisterCpuFeaturesLib: Add error handling Eric Dong
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Eric Dong @ 2017-07-14 2:49 UTC (permalink / raw)
To: edk2-devel; +Cc: Jeff Fan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
---
UefiCpuPkg/Include/Register/Msr.h | 1 +
UefiCpuPkg/Include/Register/Msr/XeonE5v2Msr.h | 91 +++++++++++++++++++++++++++
2 files changed, 92 insertions(+)
create mode 100644 UefiCpuPkg/Include/Register/Msr/XeonE5v2Msr.h
diff --git a/UefiCpuPkg/Include/Register/Msr.h b/UefiCpuPkg/Include/Register/Msr.h
index 0ac8d5b..8dbd6f7 100644
--- a/UefiCpuPkg/Include/Register/Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr.h
@@ -45,5 +45,6 @@
#include <Register/Msr/PentiumMMsr.h>
#include <Register/Msr/P6Msr.h>
#include <Register/Msr/PentiumMsr.h>
+#include <Register/Msr/XeonE5v2Msr.h>
#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE5v2Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE5v2Msr.h
new file mode 100644
index 0000000..29ba125
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE5v2Msr.h
@@ -0,0 +1,91 @@
+/** @file
+ MSR Definitions for Intel(R) Xeon(R) Processor E5 v2 Family.
+
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+ are provided for MSRs that contain one or more bit fields. If the MSR value
+ returned is a single 32-bit or 64-bit value, then a data structure is not
+ provided for that MSR.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.
+
+**/
+
+#ifndef __XEON_E5_V2_MSR_H__
+#define __XEON_E5_V2_MSR_H__
+
+#include <Register/ArchitecturalMsr.h>
+
+/**
+ Is Intel(R) Xeon(R) Processor E5 V2 Family?
+
+ @param DisplayFamily Display Family ID
+ @param DisplayModel Display Model ID
+
+ DisplayModel == 0x3E Intel Xeon processors E5 V2
+
+ @retval TRUE Yes, it is.
+ @retval FALSE No, it isn't.
+**/
+#define IS_XEON_E5_V2_PROCESSOR(DisplayFamily, DisplayModel) \
+ (DisplayFamily == 0x06 && \
+ ( \
+ DisplayModel == 0x3E \
+ ) \
+ )
+
+#define MSR_XEON_E5_V2_PIN_CTL 0x0000004E
+
+/**
+ MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] LockOut (R/WO) 1 = Locked; 0 = unlocked
+ /// Set 1 to prevent further writes to MSR_PPIN_CTL. Writing 1 to
+ /// MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit 1] is
+ /// clear, Default is 0.
+ /// BIOS should provide an opt-in menu to enable the user to turn on
+ /// MSR_PPIN_CTL[bit 1] for privileged inventory initialization agent to
+ /// access MSR_PPIN. After reading MSR_PPIN, the privileged
+ /// inventory initialization agent should write '1b' to MSR_PPIN_CTL
+ /// to disable further access to MSR_PPIN and prevent unauthorized
+ /// modification to MSR_PPIN_CTL
+ ///
+ UINT32 LockOut:1;
+ /// [Bit 1] Enable_PPIN (R/W) 1 = Enabled; 0 = Disabled
+ /// If 1, enables MSR_PPIN to be accessible using RDMSR. Once set,
+ /// attempt to write 1 to MSR_PPIN_CTL[bit 0] will cause #GP.
+ /// If 0, an attempt to read MSR_PPIN will cause #GP. Default is 0
+ ///
+ UINT32 EnablePpin:1;
+ UINT32 Reserved1:30;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_E5_V2_PIN_CTL_REGISTER;
+
+#define MSR_XEON_E5_V2_PLATFORM_INFO 0x000000CE
+
+#endif
\ No newline at end of file
--
2.7.0.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Patch 2/4] UefiCpuPkg RegisterCpuFeaturesLib: Add error handling.
2017-07-14 2:49 [Patch 0/4] Enable PPIN Cpu feature Eric Dong
2017-07-14 2:49 ` [Patch 1/4] UefiCpuPkg: Add PPIN related MSR for Xeon E5 Eric Dong
@ 2017-07-14 2:49 ` Eric Dong
2017-07-14 2:49 ` [Patch 3/4] UefiCpuPkg: Add feature definition for PPIN Eric Dong
2017-07-14 2:49 ` [Patch 4/4] UefiCpuPkg CpuCommonFeaturesLib: Enable Ppin feature Eric Dong
3 siblings, 0 replies; 5+ messages in thread
From: Eric Dong @ 2017-07-14 2:49 UTC (permalink / raw)
To: edk2-devel; +Cc: Jeff Fan
Disable CPU feature may return error, add error handling
code to handle it instead of assert it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
---
.../Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index e91a438..7a76730 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -536,7 +536,14 @@ AnalysisProcessorFeatures (
}
} else {
Status = CpuFeatureInOrder->InitializeFunc (ProcessorNumber, CpuInfo, CpuFeatureInOrder->ConfigData, FALSE);
- ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ if (CpuFeatureInOrder->FeatureName != NULL) {
+ DEBUG ((DEBUG_WARN, "Warning :: Failed to enable Feature Name = %a.\n", CpuFeatureInOrder->FeatureName));
+ } else {
+ DEBUG ((DEBUG_WARN, "Warning :: Failed to enable Feature Mask = "));
+ DumpCpuFeatureMask (CpuFeatureInOrder->FeatureMask);
+ }
+ }
}
Entry = Entry->ForwardLink;
}
--
2.7.0.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Patch 3/4] UefiCpuPkg: Add feature definition for PPIN.
2017-07-14 2:49 [Patch 0/4] Enable PPIN Cpu feature Eric Dong
2017-07-14 2:49 ` [Patch 1/4] UefiCpuPkg: Add PPIN related MSR for Xeon E5 Eric Dong
2017-07-14 2:49 ` [Patch 2/4] UefiCpuPkg RegisterCpuFeaturesLib: Add error handling Eric Dong
@ 2017-07-14 2:49 ` Eric Dong
2017-07-14 2:49 ` [Patch 4/4] UefiCpuPkg CpuCommonFeaturesLib: Enable Ppin feature Eric Dong
3 siblings, 0 replies; 5+ messages in thread
From: Eric Dong @ 2017-07-14 2:49 UTC (permalink / raw)
To: edk2-devel; +Cc: Jeff Fan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
---
UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
index 4aa3529..10286ed 100644
--- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
@@ -70,6 +70,7 @@
#define CPU_FEATURE_THREE_STRICK_COUNTER (32+8)
#define CPU_FEATURE_APIC_TPR_UPDATE_MESSAGE (32+9)
#define CPU_FEATURE_ENERGY_PERFORMANCE_BIAS (32+10)
+#define CPU_FEATURE_PPIN (32+11)
#define CPU_FEATURE_BEFORE_ALL BIT27
#define CPU_FEATURE_AFTER_ALL BIT28
--
2.7.0.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Patch 4/4] UefiCpuPkg CpuCommonFeaturesLib: Enable Ppin feature.
2017-07-14 2:49 [Patch 0/4] Enable PPIN Cpu feature Eric Dong
` (2 preceding siblings ...)
2017-07-14 2:49 ` [Patch 3/4] UefiCpuPkg: Add feature definition for PPIN Eric Dong
@ 2017-07-14 2:49 ` Eric Dong
3 siblings, 0 replies; 5+ messages in thread
From: Eric Dong @ 2017-07-14 2:49 UTC (permalink / raw)
To: edk2-devel; +Cc: Jeff Fan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
---
.../CpuCommonFeaturesLib/CpuCommonFeatures.h | 55 +++++++++++
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | 11 +++
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 1 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 107 +++++++++++++++++++++
4 files changed, 174 insertions(+)
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
index 9c6e0b4..c03e5ab 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
@@ -854,4 +854,59 @@ FeatureControlGetConfigData (
IN UINTN NumberOfProcessors
);
+/**
+ Detects if Protected Processor Inventory Number feature supported on current
+ processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Enhanced Intel SpeedStep feature is supported.
+ @retval FALSE Enhanced Intel SpeedStep feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+PpinSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes Protected Processor Inventory Number feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Protected Processor Inventory
+ Number feature must be enabled.
+ If FALSE, then the Protected Processor Inventory
+ Number feature must be disabled.
+
+ @retval RETURN_SUCCESS Protected Processor Inventory Number feature is
+ initialized.
+ @retval RETURN_DEVICE_ERROR Device can't change state because it has been
+ locked.
+
+**/
+RETURN_STATUS
+EFIAPI
+PpinInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
#endif
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
index 2bd32ab..b88b7d1 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
@@ -206,6 +206,17 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
+ if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) {
+ Status = RegisterCpuFeature (
+ "PPIN",
+ NULL,
+ PpinSupport,
+ PpinInitialize,
+ CPU_FEATURE_PPIN,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
return RETURN_SUCCESS;
}
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
index e68936b..202d560 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
@@ -47,6 +47,7 @@
MonitorMwait.c
PendingBreak.c
X2Apic.c
+ Ppin.c
[Packages]
MdePkg/MdePkg.dec
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
new file mode 100644
index 0000000..5c213e3
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
@@ -0,0 +1,107 @@
+/** @file
+ Protected Processor Inventory Number(PPIN) feature.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Detects if Protected Processor Inventory Number feature supported on current
+ processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Enhanced Intel SpeedStep feature is supported.
+ @retval FALSE Enhanced Intel SpeedStep feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+PpinSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ UINT64 MsrValue;
+
+ if (IS_XEON_E5_V2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ //
+ // Check whether platform support this feature.
+ //
+ MsrValue = AsmReadMsr64 (MSR_XEON_E5_V2_PLATFORM_INFO);
+ return ((MsrValue & BIT23) != 0);
+ }
+
+ return FALSE;
+}
+
+/**
+ Initializes Protected Processor Inventory Number feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Protected Processor Inventory
+ Number feature must be enabled.
+ If FALSE, then the Protected Processor Inventory
+ Number feature must be disabled.
+
+ @retval RETURN_SUCCESS Protected Processor Inventory Number feature is
+ initialized.
+ @retval RETURN_DEVICE_ERROR Device can't change state because it has been
+ locked.
+
+**/
+RETURN_STATUS
+EFIAPI
+PpinInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ MSR_XEON_E5_V2_PIN_CTL_REGISTER MsrPpinCtrl;
+
+ //
+ // Check whether device already lock this register.
+ // If already locked, just base on the request state and
+ // the current state to return the status.
+ //
+ MsrPpinCtrl.Uint64 = AsmReadMsr64 (MSR_XEON_E5_V2_PIN_CTL);
+ if (MsrPpinCtrl.Bits.LockOut != 0) {
+ return MsrPpinCtrl.Bits.EnablePpin == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR;
+ }
+
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_XEON_E5_V2_PIN_CTL,
+ MSR_XEON_E5_V2_PIN_CTL_REGISTER,
+ Bits.EnablePpin,
+ (State) ? 1 : 0
+ );
+
+ return RETURN_SUCCESS;
+}
--
2.7.0.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread