From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9EFC321B06E60 for ; Thu, 13 Jul 2017 19:47:31 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jul 2017 19:49:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,357,1496127600"; d="scan'208";a="992840976" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga003.jf.intel.com with ESMTP; 13 Jul 2017 19:49:19 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Jeff Fan Date: Fri, 14 Jul 2017 10:49:14 +0800 Message-Id: <1500000554-21960-5-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1500000554-21960-1-git-send-email-eric.dong@intel.com> References: <1500000554-21960-1-git-send-email-eric.dong@intel.com> Subject: [Patch 4/4] UefiCpuPkg CpuCommonFeaturesLib: Enable Ppin feature. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Jul 2017 02:47:31 -0000 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong Cc: Jeff Fan --- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 55 +++++++++++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | 11 +++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 1 + UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 107 +++++++++++++++++++++ 4 files changed, 174 insertions(+) create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index 9c6e0b4..c03e5ab 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -854,4 +854,59 @@ FeatureControlGetConfigData ( IN UINTN NumberOfProcessors ); +/** + Detects if Protected Processor Inventory Number feature supported on current + processor. + + @param[in] ProcessorNumber The index of the CPU executing this function. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION + structure for the CPU executing this function. + @param[in] ConfigData A pointer to the configuration buffer returned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provided in + RegisterCpuFeature(). + + @retval TRUE Enhanced Intel SpeedStep feature is supported. + @retval FALSE Enhanced Intel SpeedStep feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +PpinSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ); + +/** + Initializes Protected Processor Inventory Number feature to specific state. + + @param[in] ProcessorNumber The index of the CPU executing this function. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION + structure for the CPU executing this function. + @param[in] ConfigData A pointer to the configuration buffer returned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provided in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inventory + Number feature must be enabled. + If FALSE, then the Protected Processor Inventory + Number feature must be disabled. + + @retval RETURN_SUCCESS Protected Processor Inventory Number feature is + initialized. + @retval RETURN_DEVICE_ERROR Device can't change state because it has been + locked. + +**/ +RETURN_STATUS +EFIAPI +PpinInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ); + #endif diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index 2bd32ab..b88b7d1 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -206,6 +206,17 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) { + Status = RegisterCpuFeature ( + "PPIN", + NULL, + PpinSupport, + PpinInitialize, + CPU_FEATURE_PPIN, + CPU_FEATURE_END + ); + ASSERT_EFI_ERROR (Status); + } return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf index e68936b..202d560 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -47,6 +47,7 @@ MonitorMwait.c PendingBreak.c X2Apic.c + Ppin.c [Packages] MdePkg/MdePkg.dec diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c new file mode 100644 index 0000000..5c213e3 --- /dev/null +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c @@ -0,0 +1,107 @@ +/** @file + Protected Processor Inventory Number(PPIN) feature. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CpuCommonFeatures.h" + +/** + Detects if Protected Processor Inventory Number feature supported on current + processor. + + @param[in] ProcessorNumber The index of the CPU executing this function. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION + structure for the CPU executing this function. + @param[in] ConfigData A pointer to the configuration buffer returned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provided in + RegisterCpuFeature(). + + @retval TRUE Enhanced Intel SpeedStep feature is supported. + @retval FALSE Enhanced Intel SpeedStep feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +PpinSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ) +{ + UINT64 MsrValue; + + if (IS_XEON_E5_V2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { + // + // Check whether platform support this feature. + // + MsrValue = AsmReadMsr64 (MSR_XEON_E5_V2_PLATFORM_INFO); + return ((MsrValue & BIT23) != 0); + } + + return FALSE; +} + +/** + Initializes Protected Processor Inventory Number feature to specific state. + + @param[in] ProcessorNumber The index of the CPU executing this function. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION + structure for the CPU executing this function. + @param[in] ConfigData A pointer to the configuration buffer returned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provided in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inventory + Number feature must be enabled. + If FALSE, then the Protected Processor Inventory + Number feature must be disabled. + + @retval RETURN_SUCCESS Protected Processor Inventory Number feature is + initialized. + @retval RETURN_DEVICE_ERROR Device can't change state because it has been + locked. + +**/ +RETURN_STATUS +EFIAPI +PpinInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ) +{ + MSR_XEON_E5_V2_PIN_CTL_REGISTER MsrPpinCtrl; + + // + // Check whether device already lock this register. + // If already locked, just base on the request state and + // the current state to return the status. + // + MsrPpinCtrl.Uint64 = AsmReadMsr64 (MSR_XEON_E5_V2_PIN_CTL); + if (MsrPpinCtrl.Bits.LockOut != 0) { + return MsrPpinCtrl.Bits.EnablePpin == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR; + } + + CPU_REGISTER_TABLE_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_XEON_E5_V2_PIN_CTL, + MSR_XEON_E5_V2_PIN_CTL_REGISTER, + Bits.EnablePpin, + (State) ? 1 : 0 + ); + + return RETURN_SUCCESS; +} -- 2.7.0.windows.1