From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 50E6721D0DE68 for ; Tue, 18 Jul 2017 19:35:45 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Jul 2017 19:37:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,379,1496127600"; d="scan'208";a="1152898719" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga001.jf.intel.com with ESMTP; 18 Jul 2017 19:37:38 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Jeff Fan , Ruiyu Ni Date: Wed, 19 Jul 2017 10:37:35 +0800 Message-Id: <1500431855-11084-3-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1500431855-11084-1-git-send-email-eric.dong@intel.com> References: <1500431855-11084-1-git-send-email-eric.dong@intel.com> Subject: [Patch 2/2] MdeModulePkg SmmAccess: Update comments to follow PI spec. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Jul 2017 02:35:45 -0000 Cc: Jeff Fan Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong --- MdeModulePkg/Include/Ppi/SmmAccess.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Include/Ppi/SmmAccess.h b/MdeModulePkg/Include/Ppi/SmmAccess.h index 085ad64..d91374e 100644 --- a/MdeModulePkg/Include/Ppi/SmmAccess.h +++ b/MdeModulePkg/Include/Ppi/SmmAccess.h @@ -128,8 +128,9 @@ EFI_STATUS /// /// EFI SMM Access PPI is used to control the visibility of the SMRAM on the platform. -/// It abstracts the location and characteristics of SMRAM. The expectation is -/// that the north bridge or memory controller would publish this PPI. +/// It abstracts the location and characteristics of SMRAM. The platform should report +/// all MMRAM via PEI_SMM_ACCESS_PPI. The expectation is that the north bridge or +/// memory controller would publish this PPI. /// struct _PEI_SMM_ACCESS_PPI { PEI_SMM_OPEN Open; -- 2.7.0.windows.1