From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9B10F21AEB0AE for ; Thu, 3 Aug 2017 02:29:59 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Aug 2017 02:32:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,315,1498546800"; d="scan'208";a="119098236" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga002.jf.intel.com with ESMTP; 03 Aug 2017 02:32:09 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Jeff Fan , Ruiyu Ni , David Wei Date: Thu, 3 Aug 2017 17:32:01 +0800 Message-Id: <1501752726-14072-3-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1501752726-14072-1-git-send-email-eric.dong@intel.com> References: <1501752726-14072-1-git-send-email-eric.dong@intel.com> Subject: [Patch 2/7] Vlv2TbltDevicePkg: Enhance get mtrr mask logic. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 09:29:59 -0000 In order to not use the deprecated macro, refine get mtrr mask value logic. Cc: Jeff Fan Cc: Ruiyu Ni Cc: David Wei Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong --- Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c | 45 ++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 7 deletions(-) diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c index 99bdeb1..5a18a3f 100644 --- a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c +++ b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c @@ -70,6 +70,34 @@ GetMemorySize ( ); +/** + Initializes the valid address mask for MTRRs. + + This function initializes the valid bits mask and valid address mask for MTRRs. + +**/ +UINT64 +InitializeAddressMtrrMask ( + VOID + ) +{ + UINT32 RegEax; + UINT8 PhysicalAddressBits; + UINT64 ValidMtrrBitsMask; + + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + + if (RegEax >= 0x80000008) { + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); + + PhysicalAddressBits = (UINT8) RegEax; + } else { + PhysicalAddressBits = 36; + } + + ValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1; + return (ValidMtrrBitsMask & 0xfffffffffffff000ULL); +} EFI_STATUS EFIAPI @@ -89,6 +117,7 @@ SetPeiCacheMode ( UINT64 HighMemoryLength; UINT8 Index; MTRR_SETTINGS MtrrSetting; + UINT64 ValidMtrrAddressMask; // // Load Cache PPI @@ -124,6 +153,8 @@ SetPeiCacheMode ( &BootMode ); + ValidMtrrAddressMask = InitializeAddressMtrrMask (); + // // Determine memory usage // @@ -166,15 +197,15 @@ SetPeiCacheMode ( // Index = 0; MtrrSetting.Variables.Mtrr[0].Base = (FixedPcdGet32 (PcdFlashAreaBaseAddress) | CacheWriteProtected); - MtrrSetting.Variables.Mtrr[0].Mask = ((~((UINT64)(FixedPcdGet32 (PcdFlashAreaSize) - 1))) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED; + MtrrSetting.Variables.Mtrr[0].Mask = ((~((UINT64)(FixedPcdGet32 (PcdFlashAreaSize) - 1))) & ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED; Index ++; MemOverflow =0; while (MaxMemoryLength > MemOverflow){ - MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack; + MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & ValidMtrrAddressMask) | CacheWriteBack; MemoryLength = MaxMemoryLength - MemOverflow; MemoryLength = GetPowerOfTwo64 (MemoryLength); - MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED; + MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED; MemOverflow += MemoryLength; Index++; @@ -185,15 +216,15 @@ SetPeiCacheMode ( while (MaxMemoryLength != MemoryLength) { MemoryLengthUc = GetPowerOfTwo64 (MaxMemoryLength - MemoryLength); - MtrrSetting.Variables.Mtrr[Index].Base = ((MaxMemoryLength - MemoryLengthUc) & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheUncacheable; - MtrrSetting.Variables.Mtrr[Index].Mask= ((~(MemoryLengthUc - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED; + MtrrSetting.Variables.Mtrr[Index].Base = ((MaxMemoryLength - MemoryLengthUc) & ValidMtrrAddressMask) | CacheUncacheable; + MtrrSetting.Variables.Mtrr[Index].Mask= ((~(MemoryLengthUc - 1)) & ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED; MaxMemoryLength -= MemoryLengthUc; Index++; } MemOverflow =0x100000000; while (HighMemoryLength > 0) { - MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack; + MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & ValidMtrrAddressMask) | CacheWriteBack; MemoryLength = HighMemoryLength; MemoryLength = GetPowerOfTwo64 (MemoryLength); @@ -201,7 +232,7 @@ SetPeiCacheMode ( MemoryLength = MemOverflow; } - MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED; + MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED; MemOverflow += MemoryLength; HighMemoryLength -= MemoryLength; -- 2.7.0.windows.1