From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 92F7A21AEB0B0 for ; Thu, 3 Aug 2017 02:30:00 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Aug 2017 02:32:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,315,1498546800"; d="scan'208";a="119098248" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga002.jf.intel.com with ESMTP; 03 Aug 2017 02:32:10 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Jeff Fan , Ruiyu Ni Date: Thu, 3 Aug 2017 17:32:02 +0800 Message-Id: <1501752726-14072-4-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1501752726-14072-1-git-send-email-eric.dong@intel.com> References: <1501752726-14072-1-git-send-email-eric.dong@intel.com> Subject: [Patch 3/7] UefiCpuPkg CpuDxe: Enhance get mtrr mask logic. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 09:30:00 -0000 In order to not use the deprecated macro, refine get mtrr mask value logic. Cc: Jeff Fan Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong --- UefiCpuPkg/CpuDxe/CpuDxe.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index 8680656..6218670 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -25,8 +25,8 @@ BOOLEAN InterruptState = FALSE; EFI_HANDLE mCpuHandle = NULL; BOOLEAN mIsFlushingGCD; -UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS; -UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK; +UINT64 mValidMtrrAddressMask; +UINT64 mValidMtrrBitsMask; UINT64 mTimerPeriod = 0; FIXED_MTRR mFixedMtrrTable[] = { @@ -510,13 +510,12 @@ InitializeMtrrMask ( AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); PhysicalAddressBits = (UINT8) RegEax; - - mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1; - mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL; } else { - mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK; - mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS; + PhysicalAddressBits = 36; } + + mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1; + mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL; } /** -- 2.7.0.windows.1