From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-x233.google.com (mail-lf0-x233.google.com [IPv6:2a00:1450:4010:c07::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9759421E62BB2 for ; Fri, 1 Sep 2017 04:11:35 -0700 (PDT) Received: by mail-lf0-x233.google.com with SMTP id z12so8023760lfd.3 for ; Fri, 01 Sep 2017 04:14:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zO0zdmC70Bmyvam3ctAit/ln9j72C/7pAc51QDZ+rsU=; b=lQc1zHrQxZGIlgIg+juzagHbOSNl9V0vpFkOo35VBcmBbNh5lpPl3gWkv1kiiEXw1w 7aVmNTm7KjejI5oY6kM2z95nEODimIshZDIQndx/4gHJWBAcu1g+Emr+/MbiSj2Y3Up0 A4uMKqr+ntiAk+zM5JGHnAIOsQdURn61BIk32lP2vC+DTZRM6Kw47KSPBV+qFSFCUxnv gNt/2VIHuN8cduY55zeZY7gQGC+pAQEHGB4cMkUd7eguP1rru31Q8nyrpemiQ4QBkb0Y kZ/3zN49zNWMhjxtT76+slypLTEekUfVBPkR7bVYrW3+9VAA7mD57U5M3wWFgGXid8r1 aeQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zO0zdmC70Bmyvam3ctAit/ln9j72C/7pAc51QDZ+rsU=; b=uFHmtL/PJWZqAPOgJoTpU1yheUlwcY5n2Dpl7WEcemuh3Sgkpb9D57j86NJri0uGsl 6MADeJOdM0SZzS6OLskE6jItGGzvM/xx3HOZlPqwAkWmWrhL4zmvu6LUEaShkBTs1Ynt vBSVdwQDvmmk5L03N+23+XS0IBVTJ54L5va315SfB6JLan4CZz7lG+BxO26n+WTZe5LC uHU0vvwZXZ8zaSsgjM5xnVlk12ruebcs2VOAfI87yv2HQVeoc+lECVsX7F51QLlQPWx4 lhTlvDlFGgzvpgIy8im0udRcTwrcnChbCaJDIIAvtP/+BH84rGLVzCwVuHmaCtTdrvvx FNZQ== X-Gm-Message-State: AHPjjUj8ReEE/RkKWBt+zbF/U6E6fvr9CzZxpPTaALc1M03O+9oHEqGG P51Z911M91AaZ0KB3aEyQQ== X-Google-Smtp-Source: ADKCNb5CV2ZMUtZH44xH+4ZEX7nsNDTAjmBviIXNOFeB1DmOtg0nOR6wrRONRfbgmAYLFfA486Jgyg== X-Received: by 10.25.23.97 with SMTP id n94mr727223lfi.93.1504264455204; Fri, 01 Sep 2017 04:14:15 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id i11sm442673lfk.79.2017.09.01.04.14.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 04:14:13 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, agraf@suse.de, mw@semihalf.com, jsd@semihalf.com Date: Fri, 1 Sep 2017 13:17:53 +0200 Message-Id: <1504264679-13613-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504264679-13613-1-git-send-email-mw@semihalf.com> References: <1504264679-13613-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v2 1/7] Drivers/Net/Pp2Dxe: Move registers' description to macros X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Sep 2017 11:11:36 -0000 Registers' offset are constant for each PP2 controller instance, so use macros with relative addresses for their description. This allowed to remove 5 PCD's and will ease enabling second controller on Armada8k. Update PortingGuide accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada70x0.dsc | 6 ------ Platform/Marvell/Documentation/PortingGuide/Pp2.txt | 21 --------------------- Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h | 10 ++++++++++ Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 12 ++++++------ Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 6 ------ Platform/Marvell/Marvell.dec | 6 ------ 6 files changed, 16 insertions(+), 45 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc index ccfd43c..d77e0b6 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -122,18 +122,12 @@ #NET gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 } gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333 - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0xf2130e00 - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0x1000 gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x1, 0x1, 0x0 } gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x3, 0x4, 0x3 } gMarvellTokenSpaceGuid.PcdPp2NumPorts|3 gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0xf2441000 gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000 - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0xf212A200 - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0xf2130f00 - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0x1000 #PciEmulation gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 } diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt index c1554a6..3c2f418 100644 --- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt +++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt @@ -34,26 +34,5 @@ PHY_SPEED (in Mbps) is defined as follows: Base address of shared register space of PP2: gMarvellTokenSpaceGuid.PcdPp2SharedAddress -Spacing between consecutive GMAC register spaces: - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize - -Base address of GMAC: - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress - -Spacing between consecutive XLG register spaces: - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize - -Base address of XLG: - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress - -Base address of RFU1: - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress - -Base address of SMI: - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress - TCLK frequency in Hz: gMarvellTokenSpaceGuid.PcdPp2ClockFrequency - -GMAC and XLG addresses are computed as follows: - address = base_address + dev_size * gop_index diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h index f283db2..868be53 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h @@ -39,6 +39,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define BIT(nr) (1 << (nr)) #endif +/* PP2v2 registers offsets */ +#define MVPP22_SMI_OFFSET 0x12a200 +#define MVPP22_MPCS_OFFSET 0x130000 +#define MVPP22_XPCS_OFFSET 0x130400 +#define MVPP22_GMAC_OFFSET 0x130e00 +#define MVPP22_GMAC_REG_SIZE 0x1000 +#define MVPP22_XLG_OFFSET 0x130f00 +#define MVPP22_XLG_REG_SIZE 0x1000 +#define MVPP22_RFU1_OFFSET 0x441000 + /* RX Fifo Registers */ #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c index 1e2ccd0..d53f3b7 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -1141,10 +1141,6 @@ Pp2DxeParsePortPcd ( Pp2Context->Port.PhyInterface = PhyConnectionTypes[Pp2Context->Instance]; Pp2Context->Port.AlwaysUp = AlwaysUp[Pp2Context->Instance]; Pp2Context->Port.Speed = Speed[Pp2Context->Instance]; - Pp2Context->Port.GmacBase = PcdGet64 (PcdPp2GmacBaseAddress) + - PcdGet32 (PcdPp2GmacDevSize) * Pp2Context->Port.GopIndex; - Pp2Context->Port.XlgBase = PcdGet64 (PcdPp2XlgBaseAddress) + - PcdGet32 (PcdPp2XlgDevSize) * Pp2Context->Port.GopIndex; } EFI_STATUS @@ -1174,8 +1170,8 @@ Pp2DxeInitialise ( } Mvpp2Shared->Base = PcdGet64 (PcdPp2SharedAddress); - Mvpp2Shared->Rfu1Base = PcdGet64 (PcdPp2Rfu1BaseAddress); - Mvpp2Shared->SmiBase = PcdGet64 (PcdPp2SmiBaseAddress); + Mvpp2Shared->Rfu1Base = Mvpp2Shared->Base + MVPP22_RFU1_OFFSET; + Mvpp2Shared->SmiBase = Mvpp2Shared->Base + MVPP22_SMI_OFFSET; Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency); /* Prepare buffers */ @@ -1259,6 +1255,10 @@ Pp2DxeInitialise ( Pp2Context->Port.TxpNum = 1; Pp2Context->Port.Priv = Mvpp2Shared; Pp2Context->Port.FirstRxq = 4 * Pp2Context->Instance; + Pp2Context->Port.GmacBase = Mvpp2Shared->Base + MVPP22_GMAC_OFFSET + + MVPP22_GMAC_REG_SIZE * Pp2Context->Port.GopIndex; + Pp2Context->Port.XlgBase = Mvpp2Shared->Base + MVPP22_XLG_OFFSET + + MVPP22_XLG_REG_SIZE * Pp2Context->Port.GopIndex; /* Gather accumulated configuration data of all ports' MAC's */ NetCompConfig |= MvpPp2xGop110NetcCfgCreate(&Pp2Context->Port); diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index 9052fe2..ecd82b6 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -74,18 +74,12 @@ gMarvellTokenSpaceGuid.PcdPhyConnectionTypes gMarvellTokenSpaceGuid.PcdPhySmiAddresses gMarvellTokenSpaceGuid.PcdPp2ClockFrequency - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed gMarvellTokenSpaceGuid.PcdPp2NumPorts gMarvellTokenSpaceGuid.PcdPp2PortIds - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress gMarvellTokenSpaceGuid.PcdPp2SharedAddress - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize [Depex] TRUE diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 5cbf0c3..9e2f706 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -170,18 +170,12 @@ #NET gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024 gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|0|UINT32|0x3000026 - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0|UINT64|0x3000027 - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0|UINT32|0x3000028 gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029 gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B gMarvellTokenSpaceGuid.PcdPp2NumPorts|0|UINT32|0x300002D gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0|UINT64|0x300002E gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0|UINT64|0x300002F - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0|UINT64|0x3000030 - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0|UINT64|0x3000031 - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0|UINT32|0x3000032 #PciEmulation gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033 -- 1.8.3.1