From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-x22a.google.com (mail-lf0-x22a.google.com [IPv6:2a00:1450:4010:c07::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1FA7821E74907 for ; Fri, 1 Sep 2017 04:11:40 -0700 (PDT) Received: by mail-lf0-x22a.google.com with SMTP id d17so8064833lfe.1 for ; Fri, 01 Sep 2017 04:14:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FQLB7LTx57hct95H6W/FFEC04MZBc1kP3J0UbcCjXKo=; b=XmGYdbVfkl1sXHD07Tv5bjdiU4eQVSr6z9TZOZ5WXgCcOINalWxvV84W65t+zP4uOK JT72Kdm7FwtY95cdSjSU6+icpBxoCkXXbnuj/HdahoXbcWsyxU/xryxve+OCERq3XOsL zAD/ZG0lJmi8XvRrpsK/SIAmHSIT8D3ebCE2p5DjPhJzwVPQDmrXG7Hj+U8HFY3laKPv 3FQgoFbhCDjG3sKQd5ga7tygDbq/FBJDUNJctkzjbdHc7iALEDdywBAPPcEIQf3hy7vW jPVCw5hpvFljM4fqF1HKtgeV4BY9Wyu7K9v4siptAKKyzn2f/0uepvyCnnyL25vC2j24 289g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FQLB7LTx57hct95H6W/FFEC04MZBc1kP3J0UbcCjXKo=; b=EqHWnbCOoYP09ZFJt7PPpB9rV4GFTlHy8OP4MgwiwnvG3LLKi/Dqt6uaIzTVNJzHBt SYxWiAIwFpx7SzzGfk8RFNjSbs6ffSI7E1V72ZlkSVSJYCHE/kbujTDMkdYy2yWhCG0y 9WQDkdx91mpTwx2m88M9C3z+Huq4DiGFz3J9upMgC7HCJCvu1ZlAp1O3NOKcc8W7yHoS kawaipBttoGxDG/W4tHDgFZ4rCJy2JQruJWDesynEGBHqRT+z3X3rmoWQuexaolEg9zJ FMjS8kCXRVuI/nkDznf0oVGfh09vCxFLhuCylK0mX5hrTAiBd0Ha06RSc8OlkBTRA9LC 6uCA== X-Gm-Message-State: AHPjjUjLpaUcTXyZMe5obzq6MyukUWEgqFETTjFsE5SNKg41FxLcMhxA EuxOsZIrY1UHKXGYnSOyTw== X-Google-Smtp-Source: ADKCNb7sPae6cmLiML9wpkH4HAf32DTPuUUaIQy7KFJDK93ROJeJ+Z8HaAnXuL87i7+zNZDLEWvA1A== X-Received: by 10.46.83.5 with SMTP id h5mr649084ljb.104.1504264462530; Fri, 01 Sep 2017 04:14:22 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id i11sm442673lfk.79.2017.09.01.04.14.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 04:14:20 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, agraf@suse.de, mw@semihalf.com, jsd@semihalf.com, Joe Zhou Date: Fri, 1 Sep 2017 13:17:55 +0200 Message-Id: <1504264679-13613-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504264679-13613-1-git-send-email-mw@semihalf.com> References: <1504264679-13613-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v2 3/7] Drivers/Net/Pp2Dxe: Support multiple ethernet ports simultaneously X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Sep 2017 11:11:40 -0000 From: Joe Zhou In order to operate simultaneously properly, all ports should use their own resources instead of shared BM Pool and queues. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Joe Zhou Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c | 2 +- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 110 ++++++++++++++++--------- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h | 10 ++- 3 files changed, 77 insertions(+), 45 deletions(-) diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c index 27ae6b8..53154db 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c @@ -2747,7 +2747,7 @@ Mvpp2BmStop ( UINT32 Val, i; for (i = 0; i < MVPP2_BM_SIZE; i++) { - Mvpp2Read (Priv, MVPP2_BM_PHY_ALLOC_REG(0)); + Mvpp2Read (Priv, MVPP2_BM_PHY_ALLOC_REG(Pool)); } Val = Mvpp2Read (Priv, MVPP2_BM_POOL_CTRL_REG(Pool)); diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c index bdaf1a0..42cf0f9 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -189,32 +189,43 @@ Pp2DxeBmPoolInit ( Mvpp2BmIrqClear(Mvpp2Shared, Index); } - Mvpp2Shared->BmPools = AllocateZeroPool (sizeof(MVPP2_BMS_POOL)); + for (Index = 0; Index < MVPP2_MAX_PORT; Index++) { + Mvpp2Shared->BmPools[Index] = AllocateZeroPool (sizeof(MVPP2_BMS_POOL)); - if (Mvpp2Shared->BmPools == NULL) { - return EFI_OUT_OF_RESOURCES; - } + if (Mvpp2Shared->BmPools[Index] == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto FreePools; + } - Status = DmaAllocateAlignedBuffer (EfiBootServicesData, - EFI_SIZE_TO_PAGES (PoolSize), - MVPP2_BM_POOL_PTR_ALIGN, - (VOID **)&PoolAddr); - if (EFI_ERROR (Status)) { - goto FreePools; - } + Status = DmaAllocateAlignedBuffer (EfiBootServicesData, + EFI_SIZE_TO_PAGES (PoolSize), + MVPP2_BM_POOL_PTR_ALIGN, + (VOID **)&PoolAddr); + if (EFI_ERROR (Status)) { + goto FreeBmPools; + } - ZeroMem (PoolAddr, PoolSize); + ZeroMem (PoolAddr, PoolSize); - Mvpp2Shared->BmPools->Id = MVPP2_BM_POOL; - Mvpp2Shared->BmPools->VirtAddr = (UINT32 *)PoolAddr; - Mvpp2Shared->BmPools->PhysAddr = (UINTN)PoolAddr; + Mvpp2Shared->BmPools[Index]->Id = Index; + Mvpp2Shared->BmPools[Index]->VirtAddr = (UINT32 *)PoolAddr; + Mvpp2Shared->BmPools[Index]->PhysAddr = (UINTN)PoolAddr; - Mvpp2BmPoolHwCreate(Mvpp2Shared, Mvpp2Shared->BmPools, MVPP2_BM_SIZE); + Mvpp2BmPoolHwCreate(Mvpp2Shared, Mvpp2Shared->BmPools[Index], MVPP2_BM_SIZE); + } return EFI_SUCCESS; +FreeBmPools: + FreePool (Mvpp2Shared->BmPools[Index]); FreePools: - FreePool (Mvpp2Shared->BmPools); + while (Index-- >= 0) { + FreePool (Mvpp2Shared->BmPools[Index]); + DmaFreeBuffer ( + EFI_SIZE_TO_PAGES (PoolSize), + Mvpp2Shared->BmPools[Index]->VirtAddr + ); + } return Status; } @@ -226,22 +237,24 @@ Pp2DxeBmStart ( ) { UINT8 *Buff, *BuffPhys; - INTN Index; + INTN Index, Pool; ASSERT(BM_ALIGN >= sizeof(UINTN)); - Mvpp2BmPoolCtrl(Mvpp2Shared, MVPP2_BM_POOL, MVPP2_START); - Mvpp2BmPoolBufsizeSet(Mvpp2Shared, Mvpp2Shared->BmPools, RX_BUFFER_SIZE); + for (Pool = 0; Pool < MVPP2_MAX_PORT; Pool++) { + Mvpp2BmPoolCtrl(Mvpp2Shared, Pool, MVPP2_START); + Mvpp2BmPoolBufsizeSet(Mvpp2Shared, Mvpp2Shared->BmPools[Pool], RX_BUFFER_SIZE); - /* Fill BM pool with Buffers */ - for (Index = 0; Index < MVPP2_BM_SIZE; Index++) { - Buff = (UINT8 *)(BufferLocation.RxBuffers + (Index * RX_BUFFER_SIZE)); - if (Buff == NULL) { - return EFI_OUT_OF_RESOURCES; - } + /* Fill BM pool with Buffers */ + for (Index = 0; Index < MVPP2_BM_SIZE; Index++) { + Buff = (UINT8 *)(BufferLocation.RxBuffers[Pool] + (Index * RX_BUFFER_SIZE)); + if (Buff == NULL) { + return EFI_OUT_OF_RESOURCES; + } - BuffPhys = ALIGN_POINTER(Buff, BM_ALIGN); - Mvpp2BmPoolPut(Mvpp2Shared, MVPP2_BM_POOL, (UINTN)BuffPhys, (UINTN)BuffPhys); + BuffPhys = ALIGN_POINTER(Buff, BM_ALIGN); + Mvpp2BmPoolPut(Mvpp2Shared, Pool, (UINTN)BuffPhys, (UINTN)BuffPhys); + } } return EFI_SUCCESS; @@ -415,7 +428,7 @@ Pp2DxeLatePortInitialize ( } /* Use preallocated area */ - Port->Txqs[0].Descs = BufferLocation.TxDescs; + Port->Txqs[0].Descs = BufferLocation.TxDescs[Port->Id]; for (Queue = 0; Queue < TxqNumber; Queue++) { MVPP2_TX_QUEUE *Txq = &Port->Txqs[Queue]; @@ -431,7 +444,7 @@ Pp2DxeLatePortInitialize ( return EFI_OUT_OF_RESOURCES; } - Port->Rxqs[0].Descs = BufferLocation.RxDescs; + Port->Rxqs[0].Descs = BufferLocation.RxDescs[Port->Id]; for (Queue = 0; Queue < TxqNumber; Queue++) { MVPP2_RX_QUEUE *Rxq = &Port->Rxqs[Queue]; @@ -465,8 +478,8 @@ Pp2DxeLateInitialize ( } /* Attach pool to Rxq */ - Mvpp2RxqLongPoolSet(Port, 0, MVPP2_BM_POOL); - Mvpp2RxqShortPoolSet(Port, 0, MVPP2_BM_POOL); + Mvpp2RxqLongPoolSet(Port, 0, Port->Id); + Mvpp2RxqShortPoolSet(Port, 0, Port->Id); /* * Mark this port being fully initialized, @@ -654,9 +667,13 @@ Pp2DxeHalt ( PP2DXE_CONTEXT *Pp2Context = Context; PP2DXE_PORT *Port = &Pp2Context->Port; STATIC BOOLEAN CommonPartHalted = FALSE; + INTN Index; if (!CommonPartHalted) { - Mvpp2BmStop(Mvpp2Shared, MVPP2_BM_POOL); + for (Index = 0; Index < MVPP2_MAX_PORT; Index++) { + Mvpp2BmStop(Mvpp2Shared, Index); + } + CommonPartHalted = TRUE; } @@ -1188,13 +1205,26 @@ Pp2DxeInitialise ( ZeroMem (BufferSpace, BD_SPACE); - BufferLocation.TxDescs = BufferSpace; - BufferLocation.AggrTxDescs = (MVPP2_TX_DESC *)((UINTN)BufferSpace + MVPP2_MAX_TXD * sizeof(MVPP2_TX_DESC)); - BufferLocation.RxDescs = (MVPP2_RX_DESC *)((UINTN)BufferSpace + - (MVPP2_MAX_TXD + MVPP2_AGGR_TXQ_SIZE) * sizeof(MVPP2_TX_DESC)); - BufferLocation.RxBuffers = (DmaAddrT)(BufferSpace + - (MVPP2_MAX_TXD + MVPP2_AGGR_TXQ_SIZE) * sizeof(MVPP2_TX_DESC) + - MVPP2_MAX_RXD * sizeof(MVPP2_RX_DESC)); + for (Index = 0; Index < MVPP2_MAX_PORT; Index++) { + BufferLocation.TxDescs[Index] = (MVPP2_TX_DESC *) + (BufferSpace + Index * MVPP2_MAX_TXD * sizeof(MVPP2_TX_DESC)); + } + + BufferLocation.AggrTxDescs = (MVPP2_TX_DESC *) + ((UINTN)BufferSpace + MVPP2_MAX_TXD * MVPP2_MAX_PORT * sizeof(MVPP2_TX_DESC)); + + for (Index = 0; Index < MVPP2_MAX_PORT; Index++) { + BufferLocation.RxDescs[Index] = (MVPP2_RX_DESC *) + ((UINTN)BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_TXQ_SIZE) * + sizeof(MVPP2_TX_DESC) + Index * MVPP2_MAX_RXD * sizeof(MVPP2_RX_DESC)); + } + + for (Index = 0; Index < MVPP2_MAX_PORT; Index++) { + BufferLocation.RxBuffers[Index] = (DmaAddrT) + (BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_TXQ_SIZE) * + sizeof(MVPP2_TX_DESC) + MVPP2_MAX_RXD * MVPP2_MAX_PORT * sizeof(MVPP2_RX_DESC) + + Index * MVPP2_BM_SIZE * RX_BUFFER_SIZE); + } /* Initialize HW */ Mvpp2AxiConfig(Mvpp2Shared); diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h index 1e03a69..b85cff7 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h @@ -56,6 +56,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "Mvpp2LibHw.h" +#define MVPP2_MAX_PORT 3 + #define PP2DXE_SIGNATURE SIGNATURE_32('P', 'P', '2', 'D') #define INSTANCE_FROM_SNP(a) CR((a), PP2DXE_CONTEXT, Snp, PP2DXE_SIGNATURE) @@ -276,7 +278,7 @@ typedef struct { MVPP2_TX_QUEUE *AggrTxqs; /* BM pools */ - MVPP2_BMS_POOL *BmPools; + MVPP2_BMS_POOL *BmPools[MVPP2_MAX_PORT]; /* PRS shadow table */ MVPP2_PRS_SHADOW *PrsShadow; @@ -330,10 +332,10 @@ struct Pp2DxePort { /* Structure for preallocation for buffer */ typedef struct { - MVPP2_TX_DESC *TxDescs; + MVPP2_TX_DESC *TxDescs[MVPP2_MAX_PORT]; MVPP2_TX_DESC *AggrTxDescs; - MVPP2_RX_DESC *RxDescs; - DmaAddrT RxBuffers; + MVPP2_RX_DESC *RxDescs[MVPP2_MAX_PORT]; + DmaAddrT RxBuffers[MVPP2_MAX_PORT]; } BUFFER_LOCATION; typedef struct { -- 1.8.3.1