[platforms: PATCH v2 0/7] Armada 70x0/80x0 network improvements

[platforms: PATCH v2 0/7] Armada 70x0/80x0 network improvements

[Marcin Wojtas]

Hi,

Here's quick v2 of the patchset with following changes:
* Add RB's
* Modify Contributed-under to v1.1
* Fix line breaking around functions in 2/7:
Status = Function (aaa,
           bbb,
           ccc);

Patches are available in the github:
https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/pp2-upstream-r20170901-2

I'm looking forward to the comments or remarks.

Best regards,
Marcin

Joe Zhou (2):
  Drivers/Net/Pp2Dxe: Support multiple ethernet ports simultaneously
  Drivers/Net/Pp2Dxe: Increase amount of ingress resources

Marcin Wojtas (5):
  Drivers/Net/Pp2Dxe: Move registers' description to macros
  Drivers/Net/Pp2Dxe: Add SFI support
  Platforms/Marvell: Update ethernet ports types on A70x0 DB
  Drivers/Net/Pp2Dxe: Move devices description to MvHwDescLib
  Drivers/Net/Pp2Dxe: Enable using ports from different controllers

 Platform/Marvell/Armada/Armada70x0.dsc             |  21 +-
 .../Marvell/Documentation/PortingGuide/Pp2.txt     |  34 +--
 Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c     | 167 +++++++++++-
 Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h     |  31 +++
 Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h   |  51 +++-
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c       | 282 ++++++++++++++-------
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h       |  30 ++-
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf     |  11 +-
 Platform/Marvell/Include/Library/MvHwDescLib.h     |  26 ++
 Platform/Marvell/Include/Protocol/MvPhy.h          |   3 +-
 Platform/Marvell/Marvell.dec                       |  11 +-
 11 files changed, 503 insertions(+), 164 deletions(-)

-- 
1.8.3.1

[platforms: PATCH v2 1/7] Drivers/Net/Pp2Dxe: Move registers' description to macros

[Marcin Wojtas]

Registers' offset are constant for each PP2 controller instance,
so use macros with relative addresses for their description.
This allowed to remove 5 PCD's and will ease enabling second
controller on Armada8k. Update PortingGuide accordingly.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Marvell/Armada/Armada70x0.dsc              |  6 ------
 Platform/Marvell/Documentation/PortingGuide/Pp2.txt | 21 ---------------------
 Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h    | 10 ++++++++++
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c        | 12 ++++++------
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf      |  6 ------
 Platform/Marvell/Marvell.dec                        |  6 ------
 6 files changed, 16 insertions(+), 45 deletions(-)

diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc
index ccfd43c..d77e0b6 100644
--- a/Platform/Marvell/Armada/Armada70x0.dsc
+++ b/Platform/Marvell/Armada/Armada70x0.dsc
@@ -122,18 +122,12 @@
   #NET
   gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 }
   gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333
-  gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0xf2130e00
-  gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0x1000
   gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
   gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x1, 0x1, 0x0 }
   gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x3, 0x4, 0x3 }
   gMarvellTokenSpaceGuid.PcdPp2NumPorts|3
   gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
-  gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0xf2441000
   gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000
-  gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0xf212A200
-  gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0xf2130f00
-  gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0x1000
 
   #PciEmulation
   gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 }
diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
index c1554a6..3c2f418 100644
--- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
+++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
@@ -34,26 +34,5 @@ PHY_SPEED (in Mbps) is defined as follows:
 Base address of shared register space of PP2:
   gMarvellTokenSpaceGuid.PcdPp2SharedAddress
 
-Spacing between consecutive GMAC register spaces:
-  gMarvellTokenSpaceGuid.PcdPp2GmacDevSize
-
-Base address of GMAC:
-  gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress
-
-Spacing between consecutive XLG register spaces:
-  gMarvellTokenSpaceGuid.PcdPp2XlgDevSize
-
-Base address of XLG:
-  gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress
-
-Base address of RFU1:
-  gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress
-
-Base address of SMI:
-  gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress
-
 TCLK frequency in Hz:
   gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
-
-GMAC and XLG addresses are computed as follows:
-  address = base_address + dev_size * gop_index
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
index f283db2..868be53 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
@@ -39,6 +39,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define BIT(nr)         (1 << (nr))
 #endif
 
+/* PP2v2 registers offsets */
+#define MVPP22_SMI_OFFSET                                  0x12a200
+#define MVPP22_MPCS_OFFSET                                 0x130000
+#define MVPP22_XPCS_OFFSET                                 0x130400
+#define MVPP22_GMAC_OFFSET                                 0x130e00
+#define MVPP22_GMAC_REG_SIZE                               0x1000
+#define MVPP22_XLG_OFFSET                                  0x130f00
+#define MVPP22_XLG_REG_SIZE                                0x1000
+#define MVPP22_RFU1_OFFSET                                 0x441000
+
 /* RX Fifo Registers */
 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port)                 (0x00 + 4 * (port))
 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port)                 (0x20 + 4 * (port))
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
index 1e2ccd0..d53f3b7 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
@@ -1141,10 +1141,6 @@ Pp2DxeParsePortPcd (
   Pp2Context->Port.PhyInterface = PhyConnectionTypes[Pp2Context->Instance];
   Pp2Context->Port.AlwaysUp = AlwaysUp[Pp2Context->Instance];
   Pp2Context->Port.Speed = Speed[Pp2Context->Instance];
-  Pp2Context->Port.GmacBase = PcdGet64 (PcdPp2GmacBaseAddress) +
-                              PcdGet32 (PcdPp2GmacDevSize) * Pp2Context->Port.GopIndex;
-  Pp2Context->Port.XlgBase = PcdGet64 (PcdPp2XlgBaseAddress) +
-                             PcdGet32 (PcdPp2XlgDevSize) * Pp2Context->Port.GopIndex;
 }
 
 EFI_STATUS
@@ -1174,8 +1170,8 @@ Pp2DxeInitialise (
   }
 
   Mvpp2Shared->Base = PcdGet64 (PcdPp2SharedAddress);
-  Mvpp2Shared->Rfu1Base = PcdGet64 (PcdPp2Rfu1BaseAddress);
-  Mvpp2Shared->SmiBase = PcdGet64 (PcdPp2SmiBaseAddress);
+  Mvpp2Shared->Rfu1Base = Mvpp2Shared->Base + MVPP22_RFU1_OFFSET;
+  Mvpp2Shared->SmiBase = Mvpp2Shared->Base + MVPP22_SMI_OFFSET;
   Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency);
 
   /* Prepare buffers */
@@ -1259,6 +1255,10 @@ Pp2DxeInitialise (
     Pp2Context->Port.TxpNum = 1;
     Pp2Context->Port.Priv = Mvpp2Shared;
     Pp2Context->Port.FirstRxq = 4 * Pp2Context->Instance;
+    Pp2Context->Port.GmacBase = Mvpp2Shared->Base + MVPP22_GMAC_OFFSET +
+                                MVPP22_GMAC_REG_SIZE * Pp2Context->Port.GopIndex;
+    Pp2Context->Port.XlgBase = Mvpp2Shared->Base + MVPP22_XLG_OFFSET +
+                               MVPP22_XLG_REG_SIZE * Pp2Context->Port.GopIndex;
 
     /* Gather accumulated configuration data of all ports' MAC's */
     NetCompConfig |= MvpPp2xGop110NetcCfgCreate(&Pp2Context->Port);
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
index 9052fe2..ecd82b6 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
@@ -74,18 +74,12 @@
   gMarvellTokenSpaceGuid.PcdPhyConnectionTypes
   gMarvellTokenSpaceGuid.PcdPhySmiAddresses
   gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
-  gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress
-  gMarvellTokenSpaceGuid.PcdPp2GmacDevSize
   gMarvellTokenSpaceGuid.PcdPp2GopIndexes
   gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
   gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
   gMarvellTokenSpaceGuid.PcdPp2NumPorts
   gMarvellTokenSpaceGuid.PcdPp2PortIds
-  gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress
   gMarvellTokenSpaceGuid.PcdPp2SharedAddress
-  gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress
-  gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress
-  gMarvellTokenSpaceGuid.PcdPp2XlgDevSize
 
 [Depex]
   TRUE
diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
index 5cbf0c3..9e2f706 100644
--- a/Platform/Marvell/Marvell.dec
+++ b/Platform/Marvell/Marvell.dec
@@ -170,18 +170,12 @@
 #NET
   gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024
   gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|0|UINT32|0x3000026
-  gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0|UINT64|0x3000027
-  gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0|UINT32|0x3000028
   gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029
   gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A
   gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B
   gMarvellTokenSpaceGuid.PcdPp2NumPorts|0|UINT32|0x300002D
   gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C
-  gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0|UINT64|0x300002E
   gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0|UINT64|0x300002F
-  gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0|UINT64|0x3000030
-  gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0|UINT64|0x3000031
-  gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0|UINT32|0x3000032
 
 #PciEmulation
   gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033
-- 
1.8.3.1

[platforms: PATCH v2 2/7] Drivers/Net/Pp2Dxe: Add SFI support

[Marcin Wojtas]

Since now SerDes can be properly configured to support 10G
link, add this feature to the Armada 7k/8k network driver
as well. This patch extends low-level configuration routines
with SFI additions, which required two new fields in
PP2DXE_PORT structure (XpcsBase and MpcsBase).

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c   | 165 +++++++++++++++++++++++
 Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h   |  31 +++++
 Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h |  39 +++++-
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c     |   2 +
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h     |   4 +-
 Platform/Marvell/Include/Protocol/MvPhy.h        |   3 +-
 6 files changed, 241 insertions(+), 3 deletions(-)

diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c
index cdd0979..27ae6b8 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c
@@ -4116,6 +4116,21 @@ MvGop110PortInit (
     /* MAC unreset */
     MvGop110GmacReset (Port, UNRESET);
   break;
+  case MV_MODE_SFI:
+    /* Configure PCS */
+    MvGopXpcsModeCfg (Port, MVPP2_SFI_LANE_COUNT);
+
+    MvGopMpcsModeCfg (Port);
+
+    /* Configure MAC */
+    MvGopXlgMacModeCfg (Port);
+
+    /* PCS unreset */
+    MvGopXpcsUnreset (Port);
+
+    /* MAC unreset */
+    MvGopXlgMacUnreset (Port);
+    break;
   default:
     return -1;
   }
@@ -4512,6 +4527,104 @@ Mvpp2SmiPhyAddrCfg (
   return 0;
 }
 
+/* Set the internal mux's to the required PCS */
+EFI_STATUS
+MvGopXpcsModeCfg (
+  IN PP2DXE_PORT *Port,
+  IN INT32 NumOfLanes
+  )
+{
+  UINT8 LaneCoeff;
+
+  switch (NumOfLanes) {
+  case 1:
+  case 2:
+  case 4:
+    LaneCoeff = NumOfLanes >> 1;
+  default:
+    return EFI_INVALID_PARAMETER;
+  }
+
+  /* Configure XG MAC mode */
+  MmioAndThenOr32 (Port->Priv->XpcsBase + MVPP22_XPCS_GLOBAL_CFG_0_REG,
+    ~(MVPP22_XPCS_PCSMODE_MASK | MVPP22_XPCS_LANEACTIVE_MASK),
+    LaneCoeff << MVPP22_XPCS_LANEACTIVE_OFFS);
+
+  return EFI_SUCCESS;
+}
+
+VOID
+MvGopMpcsModeCfg (
+  IN PP2DXE_PORT *Port
+  )
+{
+  /* Configure MPCS40G COMMON CONTROL */
+  MmioAnd32 (Port->Priv->MpcsBase + MVPP22_MPCS40G_COMMON_CONTROL,
+    ~MVPP22_MPCS_FORWARD_ERROR_CORRECTION_MASK);
+
+  /* Configure MPCS CLOCK RESET */
+  MmioAndThenOr32 (Port->Priv->MpcsBase + MVPP22_MPCS_CLOCK_RESET,
+    ~(MVPP22_MPCS_CLK_DIVISION_RATIO_MASK | MVPP22_MPCS_CLK_DIV_PHASE_SET_MASK),
+    MVPP22_MPCS_CLK_DIVISION_RATIO_DEFAULT | MVPP22_MPCS_MAC_CLK_RESET_MASK |
+    MVPP22_MPCS_RX_SD_CLK_RESET_MASK | MVPP22_MPCS_TX_SD_CLK_RESET_MASK);
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+VOID
+MvGopXlgMacModeCfg (
+  IN PP2DXE_PORT *Port
+  )
+{
+  /* Configure 10G MAC mode */
+  MmioOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, MV_XLG_MAC_CTRL0_RXFCEN_MASK);
+
+  MmioAndThenOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL3_REG,
+    ~MV_XLG_MAC_CTRL3_MACMODESELECT_MASK,
+    MV_XLG_MAC_CTRL3_MACMODESELECT_10G);
+
+  MmioAndThenOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL4_REG,
+    ~(MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_MASK | MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK_MASK),
+    MV_XLG_MAC_CTRL4_FORWARD_PFC_EN_MASK | MV_XLG_MAC_CTRL4_FORWARD_802_3X_FC_EN_MASK);
+
+  /* Configure frame size limit */
+  MmioAndThenOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL1_REG,
+    ~MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_MASK,
+    MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_DEFAULT);
+
+  /* Mask all port's external interrupts */
+  MvGop110XlgPortLinkEventMask (Port);
+
+  /* Unmask link change interrupt - enable automatic status update */
+  MmioOr32 (Port->XlgBase + MV_XLG_INTERRUPT_MASK_REG,
+    MV_XLG_INTERRUPT_LINK_CHANGE_MASK | MV_XLG_SUMMARY_INTERRUPT_MASK);
+}
+
+/* Set PCS to exit from reset */
+VOID
+MvGopXpcsUnreset (
+  IN PP2DXE_PORT *Port
+  )
+{
+  MmioOr32 (Port->Priv->XpcsBase + MVPP22_XPCS_GLOBAL_CFG_0_REG, MVPP22_XPCS_PCSRESET);
+}
+
+/* Set the MAC to exit from reset */
+VOID
+MvGopXlgMacUnreset (
+  IN PP2DXE_PORT *Port
+  )
+{
+  MmioOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, MV_XLG_MAC_CTRL0_MACRESETN_MASK);
+}
+
+BOOLEAN
+MvGop110XlgLinkStatusGet (
+  IN PP2DXE_PORT *Port
+  )
+{
+  return MmioRead32 (Port->XlgBase + MV_XLG_MAC_PORT_STATUS_REG) & MV_XLG_MAC_PORT_STATUS_LINKSTATUS_MASK;
+}
+
 BOOLEAN
 MvGop110PortIsLinkUp (
   IN PP2DXE_PORT *Port
@@ -4522,6 +4635,8 @@ MvGop110PortIsLinkUp (
   case MV_MODE_SGMII:
   case MV_MODE_QSGMII:
     return MvGop110GmacLinkStatusGet (Port);
+  case MV_MODE_SFI:
+    return MvGop110XlgLinkStatusGet (Port);
   case MV_MODE_XAUI:
   case MV_MODE_RXAUI:
     return FALSE;
@@ -4546,6 +4661,30 @@ MvGop110GmacLinkStatusGet (
   return (Val & 1) ? TRUE : FALSE;
 }
 
+STATIC
+VOID
+MvGop110XlgPortEnable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  /* Enable port and MIB counters update */
+  MmioAndThenOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG,
+    ~MV_XLG_MAC_CTRL0_MIBCNTDIS_MASK,
+    MV_XLG_MAC_CTRL0_PORTEN_MASK);
+}
+
+STATIC
+VOID
+MvGop110XlgPortDisable (
+  IN PP2DXE_PORT *Port
+  )
+{
+  /* Mask all port's external interrupts */
+  MvGop110XlgPortLinkEventMask (Port);
+
+  MmioAnd32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, ~MV_XLG_MAC_CTRL0_PORTEN_MASK);
+}
+
 VOID
 MvGop110PortDisable (
   IN PP2DXE_PORT *Port
@@ -4557,6 +4696,11 @@ MvGop110PortDisable (
   case MV_MODE_QSGMII:
     MvGop110GmacPortDisable (Port);
     break;
+  case MV_MODE_XAUI:
+  case MV_MODE_RXAUI:
+  case MV_MODE_SFI:
+    MvGop110XlgPortDisable (Port);
+    break;
   default:
     return;
   }
@@ -4573,6 +4717,11 @@ MvGop110PortEnable (
   case MV_MODE_QSGMII:
     MvGop110GmacPortEnable (Port);
     break;
+  case MV_MODE_XAUI:
+  case MV_MODE_RXAUI:
+  case MV_MODE_SFI:
+    MvGop110XlgPortEnable (Port);
+    break;
   default:
     return;
   }
@@ -4622,6 +4771,15 @@ MvGop110GmacPortLinkEventMask (
   MvGop110GmacWrite (Port, MV_GMAC_INTERRUPT_SUM_MASK_REG, RegVal);
 }
 
+VOID
+MvGop110XlgPortLinkEventMask (
+  IN PP2DXE_PORT *Port
+  )
+{
+  MmioAnd32 (Port->XlgBase + MV_XLG_EXTERNAL_INTERRUPT_MASK_REG,
+    ~MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_MASK);
+}
+
 INT32
 MvGop110PortEventsMask (
   IN PP2DXE_PORT *Port
@@ -4634,6 +4792,11 @@ MvGop110PortEventsMask (
   case MV_MODE_QSGMII:
     MvGop110GmacPortLinkEventMask (Port);
     break;
+  case MV_MODE_XAUI:
+  case MV_MODE_RXAUI:
+  case MV_MODE_SFI:
+    MvGop110XlgPortLinkEventMask (Port);
+    break;
   default:
     return -1;
   }
@@ -4655,6 +4818,7 @@ MvGop110FlCfg (
     break;
   case MV_MODE_XAUI:
   case MV_MODE_RXAUI:
+  case MV_MODE_SFI:
     return 0;
   default:
     return -1;
@@ -4679,6 +4843,7 @@ MvGop110SpeedDuplexSet (
     break;
   case MV_MODE_XAUI:
   case MV_MODE_RXAUI:
+  case MV_MODE_SFI:
     break;
   default:
     return -1;
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h
index d7d5dcb..a7011f7 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h
@@ -433,6 +433,32 @@ Mvpp2SmiPhyAddrCfg (
   IN INT32 Addr
   );
 
+EFI_STATUS
+MvGopXpcsModeCfg (
+  IN PP2DXE_PORT *Port,
+  IN INT32 NumOfLanes
+  );
+
+VOID
+MvGopMpcsModeCfg (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGopXlgMacModeCfg (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGopXpcsUnreset (
+  IN PP2DXE_PORT *Port
+  );
+
+VOID
+MvGopXlgMacUnreset (
+  IN PP2DXE_PORT *Port
+  );
+
 BOOLEAN
 MvGop110PortIsLinkUp (
   IN PP2DXE_PORT *Port
@@ -473,6 +499,11 @@ MvGop110PortEventsMask (
   IN PP2DXE_PORT *Port
   );
 
+VOID
+MvGop110XlgPortLinkEventMask (
+  IN PP2DXE_PORT *Port
+  );
+
 INT32
 MvGop110FlCfg (
   IN PP2DXE_PORT *Port
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
index 868be53..52509b0 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
@@ -885,6 +885,30 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define MVPP2_PORT_CTRL4_LEDS_NUMBER_MASK    \
     (0x0000003f << MVPP2_PORT_CTRL4_LEDS_NUMBER_OFFS)
 
+/* XPCS registers */
+
+/* Global Configuration 0 */
+#define MVPP22_XPCS_GLOBAL_CFG_0_REG                   0x0
+#define MVPP22_XPCS_PCSRESET                           BIT(0)
+#define MVPP22_XPCS_PCSMODE_OFFS                       3
+#define MVPP22_XPCS_PCSMODE_MASK                       (0x3 << MVPP22_XPCS_PCSMODE_OFFS)
+#define MVPP22_XPCS_LANEACTIVE_OFFS                    5
+#define MVPP22_XPCS_LANEACTIVE_MASK                    (0x3 << MVPP22_XPCS_LANEACTIVE_OFFS)
+
+/* MPCS registers */
+
+#define MVPP22_MPCS40G_COMMON_CONTROL                  0x14
+#define MVPP22_MPCS_FORWARD_ERROR_CORRECTION_MASK      BIT(10)
+
+#define MVPP22_MPCS_CLOCK_RESET                        0x14c
+#define MVPP22_MPCS_TX_SD_CLK_RESET_MASK               BIT(0)
+#define MVPP22_MPCS_RX_SD_CLK_RESET_MASK               BIT(1)
+#define MVPP22_MPCS_MAC_CLK_RESET_MASK                 BIT(2)
+#define MVPP22_MPCS_CLK_DIVISION_RATIO_OFFS            4
+#define MVPP22_MPCS_CLK_DIVISION_RATIO_MASK            (0x7 << MVPP22_MPCS_CLK_DIVISION_RATIO_OFFS)
+#define MVPP22_MPCS_CLK_DIVISION_RATIO_DEFAULT         (0x1 << MVPP22_MPCS_CLK_DIVISION_RATIO_OFFS)
+#define MVPP22_MPCS_CLK_DIV_PHASE_SET_MASK             BIT(11)
+
 /* Descriptor ring Macros */
 #define MVPP2_QUEUE_NEXT_DESC(q, index)                   (((index) < (q)->LastDesc) ? ((index) + 1) : 0)
 
@@ -1089,6 +1113,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_OFFS    0
 #define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_MASK    \
     (0x00001fff << MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_OFFS)
+#define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_DEFAULT     0x1400
 
 #define MV_XLG_MAC_CTRL1_MACLOOPBACKEN_OFFS    13
 #define MV_XLG_MAC_CTRL1_MACLOOPBACKEN_MASK    \
@@ -1167,7 +1192,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     (0x00000001 << MV_XLG_MAC_PORT_STATUS_PFC_SYNC_FIFO_FULL_OFFS)
 
 /* Port Fifos Thresholds Configuration */
-#define MV_XLG_PORT_FIFOS_THRS_CFG_REG                    (0x001)
+#define MV_XLG_PORT_FIFOS_THRS_CFG_REG                    (0x0010)
 #define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_OFFS    0
 #define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_MASK    \
     (0x0000001f << MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_OFFS)
@@ -1193,6 +1218,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS    13
 #define MV_XLG_MAC_CTRL3_MACMODESELECT_MASK    \
     (0x00000007 << MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS)
+#define MV_XLG_MAC_CTRL3_MACMODESELECT_10G     \
+    (0x00000001 << MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS)
 
 /* Port Per Prio Flow Control Status */
 #define MV_XLG_PORT_PER_PRIO_FLOW_CTRL_STATUS_REG         (0x0020)
@@ -1382,6 +1409,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_MASK    \
     (0x00000001 << MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_OFFS)
 
+#define MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK         14
+#define MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK_MASK    \
+    (0x00000001 << MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK)
+
 /* Port Mac Control5 */
 #define MV_XLG_PORT_MAC_CTRL5_REG                         (0x0088)
 #define MV_XLG_MAC_CTRL5_TXIPGLENGTH_OFFS    0
@@ -1542,6 +1573,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define MV_XLG_INTERRUPT_CAUSE_REG                        (0x0014)
 /* Port Interrupt Mask */
 #define MV_XLG_INTERRUPT_MASK_REG                         (0x0018)
+#define MV_XLG_SUMMARY_INTERRUPT_OFFSET      0
+#define MV_XLG_SUMMARY_INTERRUPT_MASK        \
+    (0x1 << MV_XLG_SUMMARY_INTERRUPT_OFFSET)
 #define MV_XLG_INTERRUPT_LINK_CHANGE_OFFS    1
 #define MV_XLG_INTERRUPT_LINK_CHANGE_MASK    \
     (0x1 << MV_XLG_INTERRUPT_LINK_CHANGE_OFFS)
@@ -1926,6 +1960,9 @@ typedef struct {
 #define MVPP2_B_HDR_INFO_LAST_MASK    BIT(12)
 #define MVPP2_B_HDR_INFO_IS_LAST(info)    ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
 
+/* SerDes */
+#define MVPP2_SFI_LANE_COUNT          1
+
 /* Net Complex */
 enum MvNetcTopology {
   MV_NETC_GE_MAC0_RXAUI_L23 = BIT(0),
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
index d53f3b7..bdaf1a0 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
@@ -1171,6 +1171,8 @@ Pp2DxeInitialise (
 
   Mvpp2Shared->Base = PcdGet64 (PcdPp2SharedAddress);
   Mvpp2Shared->Rfu1Base = Mvpp2Shared->Base + MVPP22_RFU1_OFFSET;
+  Mvpp2Shared->XpcsBase = Mvpp2Shared->Base + MVPP22_XPCS_OFFSET;
+  Mvpp2Shared->MpcsBase = Mvpp2Shared->Base + MVPP22_MPCS_OFFSET;
   Mvpp2Shared->SmiBase = Mvpp2Shared->Base + MVPP22_SMI_OFFSET;
   Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency);
 
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
index a179638..1e03a69 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
@@ -116,6 +116,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define MV_MODE_RGMII                       PHY_CONNECTION_RGMII
 #define MV_MODE_XAUI                        PHY_CONNECTION_XAUI
 #define MV_MODE_RXAUI                       PHY_CONNECTION_RXAUI
+#define MV_MODE_SFI                         PHY_CONNECTION_SFI
 #define MV_MODE_QSGMII                      100
 #define PP2DXE_MAX_PHY                      2
 
@@ -263,9 +264,10 @@ typedef struct Pp2DxePort PP2DXE_PORT;
 typedef struct {
   /* Shared registers' base addresses */
   UINT64 Base;
+  UINT64 MpcsBase;
   UINT64 Rfu1Base;
   UINT64 SmiBase;
-  VOID *LmsBase;
+  UINT64 XpcsBase;
 
   /* List of pointers to Port structures */
   PP2DXE_PORT **PortList;
diff --git a/Platform/Marvell/Include/Protocol/MvPhy.h b/Platform/Marvell/Include/Protocol/MvPhy.h
index 43a9e0b..a91759a 100644
--- a/Platform/Marvell/Include/Protocol/MvPhy.h
+++ b/Platform/Marvell/Include/Protocol/MvPhy.h
@@ -47,7 +47,8 @@ typedef enum {
   PHY_CONNECTION_SGMII,
   PHY_CONNECTION_RTBI,
   PHY_CONNECTION_XAUI,
-  PHY_CONNECTION_RXAUI
+  PHY_CONNECTION_RXAUI,
+  PHY_CONNECTION_SFI
 } PHY_CONNECTION;
 
 typedef enum {
-- 
1.8.3.1

[platforms: PATCH v2 3/7] Drivers/Net/Pp2Dxe: Support multiple ethernet ports simultaneously

[Marcin Wojtas]

From: Joe Zhou <shjzhou@marvell.com>

In order to operate simultaneously properly, all ports
should use their own resources instead of shared BM
Pool and queues.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Joe Zhou <shjzhou@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c |   2 +-
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c   | 110 ++++++++++++++++---------
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h   |  10 ++-
 3 files changed, 77 insertions(+), 45 deletions(-)

diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c
index 27ae6b8..53154db 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c
@@ -2747,7 +2747,7 @@ Mvpp2BmStop (
   UINT32 Val, i;
 
   for (i = 0; i < MVPP2_BM_SIZE; i++) {
-    Mvpp2Read (Priv, MVPP2_BM_PHY_ALLOC_REG(0));
+    Mvpp2Read (Priv, MVPP2_BM_PHY_ALLOC_REG(Pool));
   }
 
   Val = Mvpp2Read (Priv, MVPP2_BM_POOL_CTRL_REG(Pool));
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
index bdaf1a0..42cf0f9 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
@@ -189,32 +189,43 @@ Pp2DxeBmPoolInit (
     Mvpp2BmIrqClear(Mvpp2Shared, Index);
   }
 
-  Mvpp2Shared->BmPools = AllocateZeroPool (sizeof(MVPP2_BMS_POOL));
+  for (Index = 0; Index < MVPP2_MAX_PORT; Index++) {
+    Mvpp2Shared->BmPools[Index] = AllocateZeroPool (sizeof(MVPP2_BMS_POOL));
 
-  if (Mvpp2Shared->BmPools == NULL) {
-    return EFI_OUT_OF_RESOURCES;
-  }
+    if (Mvpp2Shared->BmPools[Index] == NULL) {
+      Status = EFI_OUT_OF_RESOURCES;
+      goto FreePools;
+    }
 
-  Status = DmaAllocateAlignedBuffer (EfiBootServicesData,
-                                     EFI_SIZE_TO_PAGES (PoolSize),
-                                     MVPP2_BM_POOL_PTR_ALIGN,
-                                     (VOID **)&PoolAddr);
-  if (EFI_ERROR (Status)) {
-    goto FreePools;
-  }
+    Status = DmaAllocateAlignedBuffer (EfiBootServicesData,
+                                       EFI_SIZE_TO_PAGES (PoolSize),
+                                       MVPP2_BM_POOL_PTR_ALIGN,
+                                       (VOID **)&PoolAddr);
+    if (EFI_ERROR (Status)) {
+      goto FreeBmPools;
+    }
 
-  ZeroMem (PoolAddr, PoolSize);
+    ZeroMem (PoolAddr, PoolSize);
 
-  Mvpp2Shared->BmPools->Id = MVPP2_BM_POOL;
-  Mvpp2Shared->BmPools->VirtAddr = (UINT32 *)PoolAddr;
-  Mvpp2Shared->BmPools->PhysAddr = (UINTN)PoolAddr;
+    Mvpp2Shared->BmPools[Index]->Id = Index;
+    Mvpp2Shared->BmPools[Index]->VirtAddr = (UINT32 *)PoolAddr;
+    Mvpp2Shared->BmPools[Index]->PhysAddr = (UINTN)PoolAddr;
 
-  Mvpp2BmPoolHwCreate(Mvpp2Shared, Mvpp2Shared->BmPools, MVPP2_BM_SIZE);
+    Mvpp2BmPoolHwCreate(Mvpp2Shared, Mvpp2Shared->BmPools[Index], MVPP2_BM_SIZE);
+  }
 
   return EFI_SUCCESS;
 
+FreeBmPools:
+  FreePool (Mvpp2Shared->BmPools[Index]);
 FreePools:
-  FreePool (Mvpp2Shared->BmPools);
+  while (Index-- >= 0) {
+    FreePool (Mvpp2Shared->BmPools[Index]);
+    DmaFreeBuffer (
+        EFI_SIZE_TO_PAGES (PoolSize),
+        Mvpp2Shared->BmPools[Index]->VirtAddr
+        );
+  }
   return Status;
 }
 
@@ -226,22 +237,24 @@ Pp2DxeBmStart (
   )
 {
   UINT8 *Buff, *BuffPhys;
-  INTN Index;
+  INTN Index, Pool;
 
   ASSERT(BM_ALIGN >= sizeof(UINTN));
 
-  Mvpp2BmPoolCtrl(Mvpp2Shared, MVPP2_BM_POOL, MVPP2_START);
-  Mvpp2BmPoolBufsizeSet(Mvpp2Shared, Mvpp2Shared->BmPools, RX_BUFFER_SIZE);
+  for (Pool = 0; Pool < MVPP2_MAX_PORT; Pool++) {
+    Mvpp2BmPoolCtrl(Mvpp2Shared, Pool, MVPP2_START);
+    Mvpp2BmPoolBufsizeSet(Mvpp2Shared, Mvpp2Shared->BmPools[Pool], RX_BUFFER_SIZE);
 
-  /* Fill BM pool with Buffers */
-  for (Index = 0; Index < MVPP2_BM_SIZE; Index++) {
-    Buff = (UINT8 *)(BufferLocation.RxBuffers + (Index * RX_BUFFER_SIZE));
-    if (Buff == NULL) {
-      return EFI_OUT_OF_RESOURCES;
-    }
+    /* Fill BM pool with Buffers */
+    for (Index = 0; Index < MVPP2_BM_SIZE; Index++) {
+      Buff = (UINT8 *)(BufferLocation.RxBuffers[Pool] + (Index * RX_BUFFER_SIZE));
+      if (Buff == NULL) {
+        return EFI_OUT_OF_RESOURCES;
+      }
 
-    BuffPhys = ALIGN_POINTER(Buff, BM_ALIGN);
-    Mvpp2BmPoolPut(Mvpp2Shared, MVPP2_BM_POOL, (UINTN)BuffPhys, (UINTN)BuffPhys);
+      BuffPhys = ALIGN_POINTER(Buff, BM_ALIGN);
+      Mvpp2BmPoolPut(Mvpp2Shared, Pool, (UINTN)BuffPhys, (UINTN)BuffPhys);
+    }
   }
 
   return EFI_SUCCESS;
@@ -415,7 +428,7 @@ Pp2DxeLatePortInitialize (
   }
 
   /* Use preallocated area */
-  Port->Txqs[0].Descs = BufferLocation.TxDescs;
+  Port->Txqs[0].Descs = BufferLocation.TxDescs[Port->Id];
 
   for (Queue = 0; Queue < TxqNumber; Queue++) {
     MVPP2_TX_QUEUE *Txq = &Port->Txqs[Queue];
@@ -431,7 +444,7 @@ Pp2DxeLatePortInitialize (
     return EFI_OUT_OF_RESOURCES;
   }
 
-  Port->Rxqs[0].Descs = BufferLocation.RxDescs;
+  Port->Rxqs[0].Descs = BufferLocation.RxDescs[Port->Id];
 
   for (Queue = 0; Queue < TxqNumber; Queue++) {
     MVPP2_RX_QUEUE *Rxq = &Port->Rxqs[Queue];
@@ -465,8 +478,8 @@ Pp2DxeLateInitialize (
     }
 
     /* Attach pool to Rxq */
-    Mvpp2RxqLongPoolSet(Port, 0, MVPP2_BM_POOL);
-    Mvpp2RxqShortPoolSet(Port, 0, MVPP2_BM_POOL);
+    Mvpp2RxqLongPoolSet(Port, 0, Port->Id);
+    Mvpp2RxqShortPoolSet(Port, 0, Port->Id);
 
     /*
      * Mark this port being fully initialized,
@@ -654,9 +667,13 @@ Pp2DxeHalt (
   PP2DXE_CONTEXT *Pp2Context = Context;
   PP2DXE_PORT *Port = &Pp2Context->Port;
   STATIC BOOLEAN CommonPartHalted = FALSE;
+  INTN Index;
 
   if (!CommonPartHalted) {
-    Mvpp2BmStop(Mvpp2Shared, MVPP2_BM_POOL);
+    for (Index = 0; Index < MVPP2_MAX_PORT; Index++) {
+      Mvpp2BmStop(Mvpp2Shared, Index);
+    }
+
     CommonPartHalted = TRUE;
   }
 
@@ -1188,13 +1205,26 @@ Pp2DxeInitialise (
 
   ZeroMem (BufferSpace, BD_SPACE);
 
-  BufferLocation.TxDescs = BufferSpace;
-  BufferLocation.AggrTxDescs = (MVPP2_TX_DESC *)((UINTN)BufferSpace + MVPP2_MAX_TXD * sizeof(MVPP2_TX_DESC));
-  BufferLocation.RxDescs = (MVPP2_RX_DESC *)((UINTN)BufferSpace +
-                                             (MVPP2_MAX_TXD + MVPP2_AGGR_TXQ_SIZE) * sizeof(MVPP2_TX_DESC));
-  BufferLocation.RxBuffers = (DmaAddrT)(BufferSpace +
-                                        (MVPP2_MAX_TXD + MVPP2_AGGR_TXQ_SIZE) * sizeof(MVPP2_TX_DESC) +
-                                        MVPP2_MAX_RXD * sizeof(MVPP2_RX_DESC));
+  for (Index = 0; Index < MVPP2_MAX_PORT; Index++) {
+    BufferLocation.TxDescs[Index] = (MVPP2_TX_DESC *)
+      (BufferSpace + Index * MVPP2_MAX_TXD * sizeof(MVPP2_TX_DESC));
+  }
+
+  BufferLocation.AggrTxDescs = (MVPP2_TX_DESC *)
+    ((UINTN)BufferSpace + MVPP2_MAX_TXD * MVPP2_MAX_PORT * sizeof(MVPP2_TX_DESC));
+
+  for (Index = 0; Index < MVPP2_MAX_PORT; Index++) {
+    BufferLocation.RxDescs[Index] = (MVPP2_RX_DESC *)
+      ((UINTN)BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_TXQ_SIZE) *
+      sizeof(MVPP2_TX_DESC) + Index * MVPP2_MAX_RXD * sizeof(MVPP2_RX_DESC));
+  }
+
+  for (Index = 0; Index < MVPP2_MAX_PORT; Index++) {
+    BufferLocation.RxBuffers[Index] = (DmaAddrT)
+      (BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_TXQ_SIZE) *
+      sizeof(MVPP2_TX_DESC) + MVPP2_MAX_RXD * MVPP2_MAX_PORT * sizeof(MVPP2_RX_DESC) +
+      Index * MVPP2_BM_SIZE * RX_BUFFER_SIZE);
+  }
 
   /* Initialize HW */
   Mvpp2AxiConfig(Mvpp2Shared);
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
index 1e03a69..b85cff7 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
@@ -56,6 +56,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #include "Mvpp2LibHw.h"
 
+#define MVPP2_MAX_PORT  3
+
 #define PP2DXE_SIGNATURE                    SIGNATURE_32('P', 'P', '2', 'D')
 #define INSTANCE_FROM_SNP(a)                CR((a), PP2DXE_CONTEXT, Snp, PP2DXE_SIGNATURE)
 
@@ -276,7 +278,7 @@ typedef struct {
   MVPP2_TX_QUEUE *AggrTxqs;
 
   /* BM pools */
-  MVPP2_BMS_POOL *BmPools;
+  MVPP2_BMS_POOL *BmPools[MVPP2_MAX_PORT];
 
   /* PRS shadow table */
   MVPP2_PRS_SHADOW *PrsShadow;
@@ -330,10 +332,10 @@ struct Pp2DxePort {
 
 /* Structure for preallocation for buffer */
 typedef struct {
-  MVPP2_TX_DESC *TxDescs;
+  MVPP2_TX_DESC *TxDescs[MVPP2_MAX_PORT];
   MVPP2_TX_DESC *AggrTxDescs;
-  MVPP2_RX_DESC *RxDescs;
-  DmaAddrT RxBuffers;
+  MVPP2_RX_DESC *RxDescs[MVPP2_MAX_PORT];
+  DmaAddrT RxBuffers[MVPP2_MAX_PORT];
 } BUFFER_LOCATION;
 
 typedef struct {
-- 
1.8.3.1

[platforms: PATCH v2 4/7] Drivers/Net/Pp2Dxe: Increase amount of ingress resources

[Marcin Wojtas]

From: Joe Zhou <shjzhou@marvell.com>

Increase Rx ring and BM pool size for each port, which is
helpful when dealing with more intense incoming network
traffic.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Joe Zhou <shjzhou@marvell.com
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h | 2 +-
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
index 52509b0..0ebf936 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
@@ -965,7 +965,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define MVPP2_RXQ_TOTAL_NUM                               (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
 
 /* Max number of Rx descriptors */
-#define MVPP2_MAX_RXD                                     32
+#define MVPP2_MAX_RXD                                     64
 
 /* Max number of Tx descriptors */
 #define MVPP2_MAX_TXD                                     32
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
index b85cff7..9e71ec9 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
@@ -138,7 +138,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #define MVPP2_BM_SWF_LONG_POOL(Port)       ((Port > 2) ? 2 : Port)
 #define MVPP2_BM_SWF_SHORT_POOL            3
 #define MVPP2_BM_POOL                      0
-#define MVPP2_BM_SIZE                      32
+#define MVPP2_BM_SIZE                      64
 
 /*
  * BM short pool packet Size
-- 
1.8.3.1

[platforms: PATCH v2 5/7] Platforms/Marvell: Update ethernet ports types on A70x0 DB

[Marcin Wojtas]

Modify ethernet Port0 and Port1 types to be on par with the board
settings. Initial support required extra extension boards and
converters. This patch sets ports to following settings:

* Port0 (eth0) -> SFI @ 10Gbps
* Port1 (eth1) -> SGMII over 88E1512 PHY @ 1Gbps

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Marvell/Armada/Armada70x0.dsc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc
index d77e0b6..bbe6ba5 100644
--- a/Platform/Marvell/Armada/Armada70x0.dsc
+++ b/Platform/Marvell/Armada/Armada70x0.dsc
@@ -101,8 +101,8 @@
 
   #ComPhy
   gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
-  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"
-  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5000"
+  gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1;USB3_HOST1;PCIE2"
+  gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;5000"
 
   #UtmiPhy
   gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2
@@ -115,7 +115,7 @@
   gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200
 
   #PHY
-  gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x4, 0x4, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x8, 0x4, 0x0 }
   gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
   gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
 
@@ -123,8 +123,8 @@
   gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 }
   gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333
   gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
-  gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x1, 0x1, 0x0 }
-  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x3, 0x4, 0x3 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
+  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x5, 0x3, 0x3 }
   gMarvellTokenSpaceGuid.PcdPp2NumPorts|3
   gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
   gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000
-- 
1.8.3.1

[platforms: PATCH v2 6/7] Drivers/Net/Pp2Dxe: Move devices description to MvHwDescLib

[Marcin Wojtas]

This patch introduces Pp2Dxe description, using the new structures
and template in MvHwDescLib. This change enables more flexible
addition of multiple Pp2Dxe controllers. For that purpose, static global
variables (BufferLocation and Mvpp2Shared) had to be replaced by
dynamically allocated resources. PortingGuide is updated accordingly.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Marvell/Armada/Armada70x0.dsc             |   3 +-
 .../Marvell/Documentation/PortingGuide/Pp2.txt     |   9 +-
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c       | 109 ++++++++++++++++-----
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h       |  19 ++--
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf     |   3 +-
 Platform/Marvell/Include/Library/MvHwDescLib.h     |  26 +++++
 Platform/Marvell/Marvell.dec                       |   3 +-
 7 files changed, 125 insertions(+), 47 deletions(-)

diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc
index bbe6ba5..334bfaa 100644
--- a/Platform/Marvell/Armada/Armada70x0.dsc
+++ b/Platform/Marvell/Armada/Armada70x0.dsc
@@ -121,13 +121,12 @@
 
   #NET
   gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 }
-  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333
   gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
   gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
   gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x5, 0x3, 0x3 }
   gMarvellTokenSpaceGuid.PcdPp2NumPorts|3
   gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
-  gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000
+  gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
 
   #PciEmulation
   gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 }
diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
index 3c2f418..9b829c9 100644
--- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
+++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
@@ -3,6 +3,9 @@ Pp2Dxe porting guide
 Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs
 are required to operate:
 
+Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled:
+  gMarvellTokenSpaceGuid.PcdPp2Controllers
+
 Number of ports/network interfaces:
   gMarvellTokenSpaceGuid.PcdPp2NumPorts
 
@@ -30,9 +33,3 @@ PHY_SPEED (in Mbps) is defined as follows:
   4  SPEED_2500,
   5  SPEED_10000
   } PHY_SPEED;
-
-Base address of shared register space of PP2:
-  gMarvellTokenSpaceGuid.PcdPp2SharedAddress
-
-TCLK frequency in Hz:
-  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
index 42cf0f9..8e6bfbc 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
@@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include <Library/DebugLib.h>
 #include <Library/IoLib.h>
 #include <Library/MemoryAllocationLib.h>
+#include <Library/MvHwDescLib.h>
 #include <Library/NetLib.h>
 #include <Library/PcdLib.h>
 #include <Library/UefiBootServicesTableLib.h>
@@ -53,8 +54,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #define ReturnUnlock(tpl, status) do { gBS->RestoreTPL (tpl); return (status); } while(0)
 
-STATIC MVPP2_SHARED *Mvpp2Shared;
-STATIC BUFFER_LOCATION BufferLocation;
+DECLARE_A7K8K_PP2_TEMPLATE;
+
 STATIC PP2_DEVICE_PATH Pp2DevicePathTemplate = {
   {
     {
@@ -172,7 +173,7 @@ QueueRemove (
 STATIC
 EFI_STATUS
 Pp2DxeBmPoolInit (
-  VOID
+  MVPP2_SHARED *Mvpp2Shared
   )
 {
   INTN          Index;
@@ -233,7 +234,7 @@ FreePools:
 STATIC
 EFI_STATUS
 Pp2DxeBmStart (
-  VOID
+  MVPP2_SHARED *Mvpp2Shared
   )
 {
   UINT8 *Buff, *BuffPhys;
@@ -247,7 +248,7 @@ Pp2DxeBmStart (
 
     /* Fill BM pool with Buffers */
     for (Index = 0; Index < MVPP2_BM_SIZE; Index++) {
-      Buff = (UINT8 *)(BufferLocation.RxBuffers[Pool] + (Index * RX_BUFFER_SIZE));
+      Buff = (UINT8 *)(Mvpp2Shared->BufferLocation.RxBuffers[Pool] + (Index * RX_BUFFER_SIZE));
       if (Buff == NULL) {
         return EFI_OUT_OF_RESOURCES;
       }
@@ -342,6 +343,7 @@ Pp2DxeSetupAggrTxqs (
   )
 {
   MVPP2_TX_QUEUE *AggrTxq;
+  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
 
   AggrTxq = Mvpp2Shared->AggrTxqs;
   AggrTxq->DescsPhys = (DmaAddrT)AggrTxq->Descs;
@@ -361,6 +363,7 @@ Pp2DxeOpen (
   )
 {
   PP2DXE_PORT *Port = &Pp2Context->Port;
+  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
   UINT8 MacBcast[NET_ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
   UINT8 DevAddr[NET_ETHER_ADDR_LEN];
   INTN Ret;
@@ -412,6 +415,7 @@ Pp2DxeLatePortInitialize (
   )
 {
   PP2DXE_PORT *Port = &Pp2Context->Port;
+  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
   INTN Queue;
 
   Port->TxRingSize = MVPP2_MAX_TXD;
@@ -428,7 +432,7 @@ Pp2DxeLatePortInitialize (
   }
 
   /* Use preallocated area */
-  Port->Txqs[0].Descs = BufferLocation.TxDescs[Port->Id];
+  Port->Txqs[0].Descs = Mvpp2Shared->BufferLocation.TxDescs[Port->Id];
 
   for (Queue = 0; Queue < TxqNumber; Queue++) {
     MVPP2_TX_QUEUE *Txq = &Port->Txqs[Queue];
@@ -444,7 +448,7 @@ Pp2DxeLatePortInitialize (
     return EFI_OUT_OF_RESOURCES;
   }
 
-  Port->Rxqs[0].Descs = BufferLocation.RxDescs[Port->Id];
+  Port->Rxqs[0].Descs = Mvpp2Shared->BufferLocation.RxDescs[Port->Id];
 
   for (Queue = 0; Queue < TxqNumber; Queue++) {
     MVPP2_RX_QUEUE *Rxq = &Port->Rxqs[Queue];
@@ -666,6 +670,7 @@ Pp2DxeHalt (
 {
   PP2DXE_CONTEXT *Pp2Context = Context;
   PP2DXE_PORT *Port = &Pp2Context->Port;
+  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
   STATIC BOOLEAN CommonPartHalted = FALSE;
   INTN Index;
 
@@ -737,6 +742,7 @@ Pp2SnpStationAddress (
   PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(Snp);
   PP2_DEVICE_PATH *Pp2DevicePath = Pp2Context->DevicePath;
   PP2DXE_PORT *Port = &Pp2Context->Port;
+  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
   UINT32 State = Snp->Mode->State;
   EFI_TPL SavedTpl;
   INTN Ret;
@@ -877,6 +883,7 @@ Pp2SnpTransmit (
 {
   PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(This);
   PP2DXE_PORT *Port = &Pp2Context->Port;
+  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
   MVPP2_TX_QUEUE *AggrTxq = Mvpp2Shared->AggrTxqs;
   MVPP2_TX_DESC *TxDesc;
   EFI_STATUS Status;
@@ -1002,6 +1009,7 @@ Pp2SnpReceive (
   INTN ReceivedPackets;
   PP2DXE_CONTEXT *Pp2Context = INSTANCE_FROM_SNP(This);
   PP2DXE_PORT *Port = &Pp2Context->Port;
+  MVPP2_SHARED *Mvpp2Shared = Pp2Context->Port.Priv;
   UINTN PhysAddr, VirtAddr;
   EFI_STATUS Status = EFI_SUCCESS;
   EFI_TPL SavedTpl;
@@ -1160,11 +1168,12 @@ Pp2DxeParsePortPcd (
   Pp2Context->Port.Speed = Speed[Pp2Context->Instance];
 }
 
+STATIC
 EFI_STATUS
-EFIAPI
-Pp2DxeInitialise (
-  IN EFI_HANDLE ImageHandle,
-  IN EFI_SYSTEM_TABLE *SystemTable
+Pp2DxeInitialiseController (
+  IN MVPP2_SHARED *Mvpp2Shared,
+  IN UINTN BaseAddress,
+  IN UINTN ClockFrequency
   )
 {
   PP2DXE_CONTEXT *Pp2Context = NULL;
@@ -1179,19 +1188,12 @@ Pp2DxeInitialise (
     return EFI_INVALID_PARAMETER;
   }
 
-  /* Initialize private data */
-  Mvpp2Shared = AllocateZeroPool (sizeof (MVPP2_SHARED));
-  if (Mvpp2Shared == NULL) {
-    DEBUG((DEBUG_ERROR, "Allocation fail.\n"));
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  Mvpp2Shared->Base = PcdGet64 (PcdPp2SharedAddress);
+  Mvpp2Shared->Base = BaseAddress;
   Mvpp2Shared->Rfu1Base = Mvpp2Shared->Base + MVPP22_RFU1_OFFSET;
   Mvpp2Shared->XpcsBase = Mvpp2Shared->Base + MVPP22_XPCS_OFFSET;
   Mvpp2Shared->MpcsBase = Mvpp2Shared->Base + MVPP22_MPCS_OFFSET;
   Mvpp2Shared->SmiBase = Mvpp2Shared->Base + MVPP22_SMI_OFFSET;
-  Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency);
+  Mvpp2Shared->Tclk = ClockFrequency;
 
   /* Prepare buffers */
   Status = DmaAllocateAlignedBuffer (EfiBootServicesData,
@@ -1206,21 +1208,21 @@ Pp2DxeInitialise (
   ZeroMem (BufferSpace, BD_SPACE);
 
   for (Index = 0; Index < MVPP2_MAX_PORT; Index++) {
-    BufferLocation.TxDescs[Index] = (MVPP2_TX_DESC *)
+    Mvpp2Shared->BufferLocation.TxDescs[Index] = (MVPP2_TX_DESC *)
       (BufferSpace + Index * MVPP2_MAX_TXD * sizeof(MVPP2_TX_DESC));
   }
 
-  BufferLocation.AggrTxDescs = (MVPP2_TX_DESC *)
+  Mvpp2Shared->BufferLocation.AggrTxDescs = (MVPP2_TX_DESC *)
     ((UINTN)BufferSpace + MVPP2_MAX_TXD * MVPP2_MAX_PORT * sizeof(MVPP2_TX_DESC));
 
   for (Index = 0; Index < MVPP2_MAX_PORT; Index++) {
-    BufferLocation.RxDescs[Index] = (MVPP2_RX_DESC *)
+    Mvpp2Shared->BufferLocation.RxDescs[Index] = (MVPP2_RX_DESC *)
       ((UINTN)BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_TXQ_SIZE) *
       sizeof(MVPP2_TX_DESC) + Index * MVPP2_MAX_RXD * sizeof(MVPP2_RX_DESC));
   }
 
   for (Index = 0; Index < MVPP2_MAX_PORT; Index++) {
-    BufferLocation.RxBuffers[Index] = (DmaAddrT)
+    Mvpp2Shared->BufferLocation.RxBuffers[Index] = (DmaAddrT)
       (BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_TXQ_SIZE) *
       sizeof(MVPP2_TX_DESC) + MVPP2_MAX_RXD * MVPP2_MAX_PORT * sizeof(MVPP2_RX_DESC) +
       Index * MVPP2_BM_SIZE * RX_BUFFER_SIZE);
@@ -1228,7 +1230,7 @@ Pp2DxeInitialise (
 
   /* Initialize HW */
   Mvpp2AxiConfig(Mvpp2Shared);
-  Pp2DxeBmPoolInit();
+  Pp2DxeBmPoolInit (Mvpp2Shared);
   Mvpp2RxFifoInit(Mvpp2Shared);
 
   Mvpp2Shared->PrsShadow = AllocateZeroPool (sizeof(MVPP2_PRS_SHADOW) * MVPP2_PRS_TCAM_SRAM_SIZE);
@@ -1245,7 +1247,7 @@ Pp2DxeInitialise (
 
   Mvpp2ClsInit(Mvpp2Shared);
 
-  Status = Pp2DxeBmStart();
+  Status = Pp2DxeBmStart (Mvpp2Shared);
   if (EFI_ERROR(Status)) {
     DEBUG((DEBUG_ERROR, "Pp2Dxe: BM start error\n"));
     return Status;
@@ -1258,7 +1260,7 @@ Pp2DxeInitialise (
     return EFI_OUT_OF_RESOURCES;
   }
 
-  Mvpp2Shared->AggrTxqs->Descs = BufferLocation.AggrTxDescs;
+  Mvpp2Shared->AggrTxqs->Descs = Mvpp2Shared->BufferLocation.AggrTxDescs;
   Mvpp2Shared->AggrTxqs->Id = 0;
   Mvpp2Shared->AggrTxqs->LogId = 0;
   Mvpp2Shared->AggrTxqs->Size = MVPP2_AGGR_TXQ_SIZE;
@@ -1316,3 +1318,56 @@ Pp2DxeInitialise (
 
   return EFI_SUCCESS;
 }
+
+EFI_STATUS
+EFIAPI
+Pp2DxeInitialise (
+  IN EFI_HANDLE ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  MVHW_PP2_DESC *Desc = &mA7k8kPp2DescTemplate;
+  UINT8 *Pp2DeviceTable, Index;
+  MVPP2_SHARED *Mvpp2Shared;
+  EFI_STATUS Status;
+
+  /* Obtain table with enabled Pp2 devices */
+  Pp2DeviceTable = (UINT8 *)PcdGetPtr (PcdPp2Controllers);
+  if (Pp2DeviceTable == NULL) {
+    DEBUG ((DEBUG_ERROR, "Missing PcdPp2Controllers\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (PcdGetSize (PcdPp2Controllers) > MVHW_MAX_PP2_DEVS) {
+    DEBUG ((DEBUG_ERROR, "Wrong PcdPp2Controllers format\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  /* Initialize enabled chips */
+  for (Index = 0; Index < PcdGetSize (PcdPp2Controllers); Index++) {
+    if (!MVHW_DEV_ENABLED (Pp2, Index)) {
+      DEBUG ((DEBUG_ERROR, "Skip Pp2 controller %d\n", Index));
+      continue;
+    }
+
+    /* Initialize private data */
+    Mvpp2Shared = AllocateZeroPool (sizeof (MVPP2_SHARED));
+    if (Mvpp2Shared == NULL) {
+      DEBUG ((DEBUG_ERROR, "Pp2Dxe #%d: Mvpp2Shared allocation fail\n", Index));
+      return EFI_OUT_OF_RESOURCES;
+    }
+
+    Status = Pp2DxeInitialiseController (
+                    Mvpp2Shared,
+                    Desc->Pp2BaseAddresses[Index],
+                    Desc->Pp2ClockFrequency[Index]
+                    );
+    if (EFI_ERROR(Status)) {
+      FreePool (Mvpp2Shared);
+      DEBUG ((DEBUG_ERROR, "Pp2Dxe #%d: Controller initialisation fail\n", Index));
+      return Status;
+    }
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
index 9e71ec9..7071cef 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
@@ -262,6 +262,14 @@ typedef struct {
 
 typedef struct Pp2DxePort PP2DXE_PORT;
 
+/* Structure for preallocation for buffer */
+typedef struct {
+  MVPP2_TX_DESC *TxDescs[MVPP2_MAX_PORT];
+  MVPP2_TX_DESC *AggrTxDescs;
+  MVPP2_RX_DESC *RxDescs[MVPP2_MAX_PORT];
+  DmaAddrT RxBuffers[MVPP2_MAX_PORT];
+} BUFFER_LOCATION;
+
 /* Shared Packet Processor resources */
 typedef struct {
   /* Shared registers' base addresses */
@@ -271,6 +279,9 @@ typedef struct {
   UINT64 SmiBase;
   UINT64 XpcsBase;
 
+  /* Preallocated buffers */
+  BUFFER_LOCATION BufferLocation;
+
   /* List of pointers to Port structures */
   PP2DXE_PORT **PortList;
 
@@ -330,14 +341,6 @@ struct Pp2DxePort {
   UINT8 FirstRxq;
 };
 
-/* Structure for preallocation for buffer */
-typedef struct {
-  MVPP2_TX_DESC *TxDescs[MVPP2_MAX_PORT];
-  MVPP2_TX_DESC *AggrTxDescs;
-  MVPP2_RX_DESC *RxDescs[MVPP2_MAX_PORT];
-  DmaAddrT RxBuffers[MVPP2_MAX_PORT];
-} BUFFER_LOCATION;
-
 typedef struct {
   MAC_ADDR_DEVICE_PATH      Pp2Mac;
   EFI_DEVICE_PATH_PROTOCOL  End;
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
index ecd82b6..b67162d 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
@@ -73,13 +73,12 @@
 [Pcd]
   gMarvellTokenSpaceGuid.PcdPhyConnectionTypes
   gMarvellTokenSpaceGuid.PcdPhySmiAddresses
-  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
+  gMarvellTokenSpaceGuid.PcdPp2Controllers
   gMarvellTokenSpaceGuid.PcdPp2GopIndexes
   gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
   gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
   gMarvellTokenSpaceGuid.PcdPp2NumPorts
   gMarvellTokenSpaceGuid.PcdPp2PortIds
-  gMarvellTokenSpaceGuid.PcdPp2SharedAddress
 
 [Depex]
   TRUE
diff --git a/Platform/Marvell/Include/Library/MvHwDescLib.h b/Platform/Marvell/Include/Library/MvHwDescLib.h
index ac8dc37..6a86865 100644
--- a/Platform/Marvell/Include/Library/MvHwDescLib.h
+++ b/Platform/Marvell/Include/Library/MvHwDescLib.h
@@ -85,6 +85,17 @@ typedef struct {
 } MVHW_NONDISCOVERABLE_DESC;
 
 //
+// PP2 NIC devices description template definition
+//
+#define MVHW_MAX_PP2_DEVS         4
+
+typedef struct {
+  UINT8 Pp2DevCount;
+  UINTN Pp2BaseAddresses[MVHW_MAX_PP2_DEVS];
+  UINTN Pp2ClockFrequency[MVHW_MAX_PP2_DEVS];
+} MVHW_PP2_DESC;
+
+//
 // RealTimeClock devices description template definition
 //
 #define MVHW_MAX_RTC_DEVS         2
@@ -153,6 +164,21 @@ MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTemplate = {\
 }
 
 //
+// Platform description of Pp2 NIC devices
+//
+#define MVHW_CP0_PP2_BASE       0xF2000000
+#define MVHW_CP1_PP2_BASE       0xF4000000
+#define MVHW_PP2_CLK_FREQ       333333333
+
+#define DECLARE_A7K8K_PP2_TEMPLATE \
+STATIC \
+MVHW_PP2_DESC mA7k8kPp2DescTemplate = {\
+  2,\
+  { MVHW_CP0_PP2_BASE, MVHW_CP1_PP2_BASE },\
+  { MVHW_PP2_CLK_FREQ, MVHW_PP2_CLK_FREQ } \
+}
+
+//
 // Platform description of RealTimeClock devices
 //
 #define MVHW_CP0_RTC0_BASE       0xF2284000
diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
index 9e2f706..e6a3621 100644
--- a/Platform/Marvell/Marvell.dec
+++ b/Platform/Marvell/Marvell.dec
@@ -169,13 +169,12 @@
 
 #NET
   gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024
-  gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|0|UINT32|0x3000026
+  gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x0 }|VOID*|0x3000028
   gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029
   gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A
   gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B
   gMarvellTokenSpaceGuid.PcdPp2NumPorts|0|UINT32|0x300002D
   gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C
-  gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0|UINT64|0x300002F
 
 #PciEmulation
   gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033
-- 
1.8.3.1

[platforms: PATCH v2 7/7] Drivers/Net/Pp2Dxe: Enable using ports from different controllers

[Marcin Wojtas]

After Pp2Dxe data migrated to MvHwDescLib, both controllers
could be used, but not at the same time. It was caused by
ports' insufficient description. This patch fixes this problem by
introducing new PCD responsible for the mapping between port and
its controller. Also it was possible to remove redundant
PcdPp2NumPorts. Update documentation accordingly.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/Marvell/Armada/Armada70x0.dsc             |  2 +-
 .../Marvell/Documentation/PortingGuide/Pp2.txt     |  4 +-
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c       | 63 ++++++++++++++--------
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h       |  1 +
 Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf     |  2 +-
 Platform/Marvell/Marvell.dec                       |  2 +-
 6 files changed, 47 insertions(+), 27 deletions(-)

diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc
index 334bfaa..f519196 100644
--- a/Platform/Marvell/Armada/Armada70x0.dsc
+++ b/Platform/Marvell/Armada/Armada70x0.dsc
@@ -124,7 +124,7 @@
   gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
   gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
   gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x5, 0x3, 0x3 }
-  gMarvellTokenSpaceGuid.PcdPp2NumPorts|3
+  gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
   gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
   gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
 
diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
index 9b829c9..f05ba27 100644
--- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
+++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
@@ -6,8 +6,8 @@ are required to operate:
 Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled:
   gMarvellTokenSpaceGuid.PcdPp2Controllers
 
-Number of ports/network interfaces:
-  gMarvellTokenSpaceGuid.PcdPp2NumPorts
+Array specifying, to which controller the port belongs to:
+  gMarvellTokenSpaceGuid.PcdPp2Port2Controller
 
 Addresses of PHY devices:
   gMarvellTokenSpaceGuid.PcdPhySmiAddresses
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
index 8e6bfbc..620bd5c 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
@@ -508,9 +508,7 @@ Pp2DxePhyInitialize (
   )
 {
   EFI_STATUS Status;
-  UINT8 *PhyAddresses;
 
-  PhyAddresses = PcdGetPtr (PcdPhySmiAddresses);
   Status = gBS->LocateProtocol (
                &gMarvellPhyProtocolGuid,
                NULL,
@@ -521,14 +519,14 @@ Pp2DxePhyInitialize (
     return Status;
   }
 
-  if (PhyAddresses[Pp2Context->Instance] == 0xff) {
+  if (Pp2Context->Port.PhyAddr == 0xff) {
     /* PHY iniitalization not required */
     return EFI_SUCCESS;
   }
 
   Status = Pp2Context->Phy->Init(
                Pp2Context->Phy,
-               PhyAddresses[Pp2Context->Instance],
+               Pp2Context->Port.PhyAddr,
                Pp2Context->Port.PhyInterface,
                &Pp2Context->PhyDev
              );
@@ -1145,14 +1143,16 @@ Pp2DxeSnpInstall (
 STATIC
 VOID
 Pp2DxeParsePortPcd (
-  IN PP2DXE_CONTEXT *Pp2Context
+  IN PP2DXE_CONTEXT *Pp2Context,
+  IN INTN Index
   )
 {
-  UINT8 *PortIds, *GopIndexes, *PhyConnectionTypes, *AlwaysUp, *Speed;
+  UINT8 *PortIds, *GopIndexes, *PhyConnectionTypes, *AlwaysUp, *Speed, *PhyAddresses;
 
   PortIds = PcdGetPtr (PcdPp2PortIds);
   GopIndexes = PcdGetPtr (PcdPp2GopIndexes);
   PhyConnectionTypes = PcdGetPtr (PcdPhyConnectionTypes);
+  PhyAddresses = PcdGetPtr (PcdPhySmiAddresses);
   AlwaysUp = PcdGetPtr (PcdPp2InterfaceAlwaysUp);
   Speed = PcdGetPtr (PcdPp2InterfaceSpeed);
 
@@ -1160,17 +1160,20 @@ Pp2DxeParsePortPcd (
   ASSERT (PcdGetSize (PcdPhyConnectionTypes) == PcdGetSize (PcdPp2PortIds));
   ASSERT (PcdGetSize (PcdPp2InterfaceAlwaysUp) == PcdGetSize (PcdPp2PortIds));
   ASSERT (PcdGetSize (PcdPp2InterfaceSpeed) == PcdGetSize (PcdPp2PortIds));
-
-  Pp2Context->Port.Id = PortIds[Pp2Context->Instance];
-  Pp2Context->Port.GopIndex = GopIndexes[Pp2Context->Instance];
-  Pp2Context->Port.PhyInterface = PhyConnectionTypes[Pp2Context->Instance];
-  Pp2Context->Port.AlwaysUp = AlwaysUp[Pp2Context->Instance];
-  Pp2Context->Port.Speed = Speed[Pp2Context->Instance];
+  ASSERT (PcdGetSize (PcdPhySmiAddresses) == PcdGetSize (PcdPp2PortIds));
+
+  Pp2Context->Port.Id = PortIds[Index];
+  Pp2Context->Port.GopIndex = GopIndexes[Index];
+  Pp2Context->Port.PhyInterface = PhyConnectionTypes[Index];
+  Pp2Context->Port.PhyAddr = PhyAddresses[Index];
+  Pp2Context->Port.AlwaysUp = AlwaysUp[Index];
+  Pp2Context->Port.Speed = Speed[Index];
 }
 
 STATIC
 EFI_STATUS
 Pp2DxeInitialiseController (
+  IN UINT8 ControllerIndex,
   IN MVPP2_SHARED *Mvpp2Shared,
   IN UINTN BaseAddress,
   IN UINTN ClockFrequency
@@ -1179,14 +1182,11 @@ Pp2DxeInitialiseController (
   PP2DXE_CONTEXT *Pp2Context = NULL;
   EFI_STATUS Status;
   INTN Index;
+  INTN PortIndex = 0;
   VOID *BufferSpace;
   UINT32 NetCompConfig = 0;
-  UINT8 NumPorts = PcdGet32 (PcdPp2NumPorts);
-
-  if (NumPorts == 0) {
-    DEBUG((DEBUG_ERROR, "Pp2Dxe: port number set to 0\n"));
-    return EFI_INVALID_PARAMETER;
-  }
+  STATIC UINT8 DeviceInstance;
+  UINT8 *Pp2PortMappingTable;
 
   Mvpp2Shared->Base = BaseAddress;
   Mvpp2Shared->Rfu1Base = Mvpp2Shared->Base + MVPP22_RFU1_OFFSET;
@@ -1265,7 +1265,18 @@ Pp2DxeInitialiseController (
   Mvpp2Shared->AggrTxqs->LogId = 0;
   Mvpp2Shared->AggrTxqs->Size = MVPP2_AGGR_TXQ_SIZE;
 
-  for (Index = 0; Index < NumPorts; Index++) {
+  Pp2PortMappingTable = (UINT8 *)PcdGetPtr (PcdPp2Port2Controller);
+
+  for (Index = 0; Index < PcdGetSize (PcdPp2Port2Controller); Index++) {
+    if (Pp2PortMappingTable[Index] != ControllerIndex) {
+      continue;
+    }
+
+    if (PortIndex++ > MVPP2_MAX_PORT) {
+      DEBUG ((DEBUG_ERROR, "Pp2Dxe: Wrong too many ports for single controller\n"));
+      return EFI_INVALID_PARAMETER;
+    }
+
     Pp2Context = AllocateZeroPool (sizeof (PP2DXE_CONTEXT));
     if (Pp2Context == NULL) {
       /*
@@ -1277,7 +1288,8 @@ Pp2DxeInitialiseController (
     }
 
     /* Instances are enumerated from 0 */
-    Pp2Context->Instance = Index;
+    Pp2Context->Instance = DeviceInstance;
+    DeviceInstance++;
 
     /* Install SNP protocol */
     Status = Pp2DxeSnpInstall(Pp2Context);
@@ -1285,10 +1297,10 @@ Pp2DxeInitialiseController (
       return Status;
     }
 
-    Pp2DxeParsePortPcd(Pp2Context);
+    Pp2DxeParsePortPcd(Pp2Context, Index);
     Pp2Context->Port.TxpNum = 1;
     Pp2Context->Port.Priv = Mvpp2Shared;
-    Pp2Context->Port.FirstRxq = 4 * Pp2Context->Instance;
+    Pp2Context->Port.FirstRxq = 4 * (PortIndex - 1);
     Pp2Context->Port.GmacBase = Mvpp2Shared->Base + MVPP22_GMAC_OFFSET +
                                 MVPP22_GMAC_REG_SIZE * Pp2Context->Port.GopIndex;
     Pp2Context->Port.XlgBase = Mvpp2Shared->Base + MVPP22_XLG_OFFSET +
@@ -1343,6 +1355,12 @@ Pp2DxeInitialise (
     return EFI_INVALID_PARAMETER;
   }
 
+  /* Check amount of declared ports */
+  if (PcdGetSize (PcdPp2Port2Controller) > Desc->Pp2DevCount * MVPP2_MAX_PORT) {
+    DEBUG ((DEBUG_ERROR, "Pp2Dxe: Wrong too many ports declared\n"));
+    return EFI_INVALID_PARAMETER;
+  }
+
   /* Initialize enabled chips */
   for (Index = 0; Index < PcdGetSize (PcdPp2Controllers); Index++) {
     if (!MVHW_DEV_ENABLED (Pp2, Index)) {
@@ -1358,6 +1376,7 @@ Pp2DxeInitialise (
     }
 
     Status = Pp2DxeInitialiseController (
+                    Index,
                     Mvpp2Shared,
                     Desc->Pp2BaseAddresses[Index],
                     Desc->Pp2ClockFrequency[Index]
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
index 7071cef..cde2995 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
@@ -327,6 +327,7 @@ struct Pp2DxePort {
   UINT16 RxRingSize;
 
   INT32 PhyInterface;
+  UINTN PhyAddr;
   BOOLEAN Link;
   BOOLEAN Duplex;
   BOOLEAN AlwaysUp;
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
index b67162d..752fcc0 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
@@ -77,7 +77,7 @@
   gMarvellTokenSpaceGuid.PcdPp2GopIndexes
   gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
   gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
-  gMarvellTokenSpaceGuid.PcdPp2NumPorts
+  gMarvellTokenSpaceGuid.PcdPp2Port2Controller
   gMarvellTokenSpaceGuid.PcdPp2PortIds
 
 [Depex]
diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
index e6a3621..4e2dd6d 100644
--- a/Platform/Marvell/Marvell.dec
+++ b/Platform/Marvell/Marvell.dec
@@ -173,7 +173,7 @@
   gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029
   gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A
   gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B
-  gMarvellTokenSpaceGuid.PcdPp2NumPorts|0|UINT32|0x300002D
+  gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0 }|VOID*|0x300002D
   gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C
 
 #PciEmulation
-- 
1.8.3.1

Re: [platforms: PATCH v2 0/7] Armada 70x0/80x0 network improvements

[Ard Biesheuvel]

On 1 September 2017 at 12:17, Marcin Wojtas <mw@semihalf.com> wrote:
> Hi,
>
> Here's quick v2 of the patchset with following changes:
> * Add RB's
> * Modify Contributed-under to v1.1
> * Fix line breaking around functions in 2/7:
> Status = Function (aaa,
>            bbb,
>            ccc);
>
> Patches are available in the github:
> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/pp2-upstream-r20170901-2
>
> I'm looking forward to the comments or remarks.
>

Pushed to edk2-platforms

Thanks,
Ard.

Re: [platforms: PATCH v2 0/7] Armada 70x0/80x0 network improvements

[Marcin Wojtas]

2017-09-01 14:07 GMT+02:00 Ard Biesheuvel <ard.biesheuvel@linaro.org>:
> On 1 September 2017 at 12:17, Marcin Wojtas <mw@semihalf.com> wrote:
>> Hi,
>>
>> Here's quick v2 of the patchset with following changes:
>> * Add RB's
>> * Modify Contributed-under to v1.1
>> * Fix line breaking around functions in 2/7:
>> Status = Function (aaa,
>>            bbb,
>>            ccc);
>>
>> Patches are available in the github:
>> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/pp2-upstream-r20170901-2
>>
>> I'm looking forward to the comments or remarks.
>>
>
> Pushed to edk2-platforms
>
> Thanks,
> Ard.

Thanks!