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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id i11sm442673lfk.79.2017.09.01.04.14.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 04:14:24 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, agraf@suse.de, mw@semihalf.com, jsd@semihalf.com Date: Fri, 1 Sep 2017 13:17:57 +0200 Message-Id: <1504264679-13613-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504264679-13613-1-git-send-email-mw@semihalf.com> References: <1504264679-13613-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v2 5/7] Platforms/Marvell: Update ethernet ports types on A70x0 DB X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Sep 2017 11:11:44 -0000 Modify ethernet Port0 and Port1 types to be on par with the board settings. Initial support required extra extension boards and converters. This patch sets ports to following settings: * Port0 (eth0) -> SFI @ 10Gbps * Port1 (eth1) -> SGMII over 88E1512 PHY @ 1Gbps Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada70x0.dsc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc index d77e0b6..bbe6ba5 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -101,8 +101,8 @@ #ComPhy gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2" - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5000" + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1;USB3_HOST1;PCIE2" + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;5000" #UtmiPhy gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 @@ -115,7 +115,7 @@ gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200 #PHY - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x4, 0x4, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x8, 0x4, 0x0 } gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE @@ -123,8 +123,8 @@ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 } gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333 gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x3, 0x4, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x5, 0x3, 0x3 } gMarvellTokenSpaceGuid.PcdPp2NumPorts|3 gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000 -- 1.8.3.1