From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E763521EA35B5 for ; Mon, 4 Sep 2017 20:26:52 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP; 04 Sep 2017 20:29:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,477,1498546800"; d="scan'208";a="147473579" Received: from jyao1-mobl.ccr.corp.intel.com ([10.239.196.73]) by fmsmga005.fm.intel.com with ESMTP; 04 Sep 2017 20:29:40 -0700 From: Jiewen Yao To: edk2-devel@lists.01.org Cc: Star Zeng Date: Tue, 5 Sep 2017 11:29:33 +0800 Message-Id: <1504582173-9088-3-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1504582173-9088-1-git-send-email-jiewen.yao@intel.com> References: <1504582173-9088-1-git-send-email-jiewen.yao@intel.com> Subject: [PATCH 2/2] IntelFramdworkModulePkg/LegacyBios: Add IoMmu Support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Sep 2017 03:26:53 -0000 If IOMMU is enabled, the legacy BIOS need allow the legacy memory access by the legacy device. The legacy memory is below 1M memory and HighPmm memory. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao --- IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf | 1 + IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h | 1 + IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c | 72 +++++++++++++++++++- 3 files changed, 73 insertions(+), 1 deletion(-) diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf index 4ca412a..48473a0 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf @@ -137,6 +137,7 @@ gEfiLegacyBiosProtocolGuid ## PRODUCES gEfiSerialIoProtocolGuid ## CONSUMES gEfiSioProtocolGuid ## CONSUMES + gEdkiiIoMmuProtocolGuid ## CONSUMES [Pcd] gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion ## CONSUMES diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h index 069646b..fe9dd74 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBiosInterface.h @@ -47,6 +47,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include #include #include +#include #include #include diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c index c4c77ec..8ffdf0c 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyPci.c @@ -41,7 +41,7 @@ BOOLEAN mIgnoreBbsUpdateFlag; BOOLEAN mVgaInstallationInProgress = FALSE; UINT32 mRomCount = 0x00; ROM_INSTANCE_ENTRY mRomEntry[ROM_MAX_ENTRIES]; - +EDKII_IOMMU_PROTOCOL *mIoMmu; /** Query shadowed legacy ROM parameters registered by RomShadow() previously. @@ -2697,6 +2697,61 @@ Done: } /** + Let IOMMU grant DMA access for the PCI device. + + @param PciHandle The EFI handle for the PCI device. + @param HostAddress The system memory address to map to the PCI controller. + @param NumberOfBytes The number of bytes to map. + + @retval EFI_SUCCESS The DMA access is granted. +**/ +EFI_STATUS +IoMmuGrantAccess ( + IN EFI_HANDLE PciHandle, + IN EFI_PHYSICAL_ADDRESS HostAddress, + IN UINTN NumberOfBytes + ) +{ + EFI_PHYSICAL_ADDRESS DeviceAddress; + VOID *Mapping; + EFI_STATUS Status; + + if (PciHandle == NULL) { + return EFI_UNSUPPORTED; + } + + Status = EFI_SUCCESS; + if (mIoMmu == NULL) { + gBS->LocateProtocol (&gEdkiiIoMmuProtocolGuid, NULL, (VOID **)&mIoMmu); + } + if (mIoMmu != NULL) { + Status = mIoMmu->Map ( + mIoMmu, + EdkiiIoMmuOperationBusMasterCommonBuffer, + (VOID *)(UINTN)HostAddress, + &NumberOfBytes, + &DeviceAddress, + &Mapping + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuMap - %r\n", Status)); + } else { + ASSERT (DeviceAddress == HostAddress); + Status = mIoMmu->SetAttribute ( + mIoMmu, + PciHandle, + Mapping, + EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "LegacyPci - IoMmuSetAttribute - %r\n", Status)); + } + } + } + return Status; +} + +/** Load a legacy PC-AT OPROM on the PciHandle device. Return information about how many disks were added by the OPROM and the shadow address and size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C: @@ -2978,6 +3033,21 @@ LegacyBiosInstallPciRom ( RuntimeImageLength = Pcir->MaxRuntimeImageLength * 512; } } + + // + // Grant access for below 1M + // BDA/EBDA/LowPMM and scratch memory for OPROM. + // + IoMmuGrantAccess (PciHandle, 0, SIZE_1MB); + // + // Grant access for HiPmm + // + IoMmuGrantAccess ( + PciHandle, + Private->IntThunk->EfiToLegacy16InitTable.HiPmmMemory, + Private->IntThunk->EfiToLegacy16InitTable.HiPmmMemorySizeInBytes + ); + // // Shadow and initialize the OpROM. // -- 2.7.4.windows.1