From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D1F9421E97806 for ; Thu, 7 Sep 2017 04:10:28 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Sep 2017 04:13:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,358,1500966000"; d="scan'208";a="126455847" Received: from shwdeopenpsi068.ccr.corp.intel.com ([10.239.9.31]) by orsmga004.jf.intel.com with ESMTP; 07 Sep 2017 04:13:18 -0700 From: Star Zeng To: edk2-devel@lists.01.org Cc: Star Zeng , Alexei Fedorov , Ruiyu Ni Date: Thu, 7 Sep 2017 19:13:15 +0800 Message-Id: <1504782795-51684-1-git-send-email-star.zeng@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 Subject: [PATCH] MdeModulePkg Xhci: Correct description of Timeout param in XhciReg.h X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Sep 2017 11:10:29 -0000 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=653 Correct description of Timeout param in XhciReg.h to be matched with XhciReg.c. Cc: Alexei Fedorov Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng --- MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 10 +++++----- MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h index b748c8d39739..838a44628c27 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h @@ -2,7 +2,7 @@ This file contains the register definition of XHCI host controller. -Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.
+Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -399,7 +399,7 @@ XhcClearOpRegBit ( @param Offset The offset of the operational register. @param Bit The bit of the register to wait for. @param WaitToSet Wait the bit to set or clear. - @param Timeout The time to wait before abort (in microsecond, us). + @param Timeout The time to wait before abort (in millisecond, ms). @retval EFI_SUCCESS The bit successfully changed by host controller. @retval EFI_TIMEOUT The time out occurred. @@ -521,7 +521,7 @@ XhcIsSysError ( Reset the XHCI host controller. @param Xhc The XHCI Instance. - @param Timeout Time to wait before abort (in microsecond, us). + @param Timeout Time to wait before abort (in millisecond, ms). @retval EFI_SUCCESS The XHCI host controller is reset. @return Others Failed to reset the XHCI before Timeout. @@ -537,7 +537,7 @@ XhcResetHC ( Halt the XHCI host controller. @param Xhc The XHCI Instance. - @param Timeout Time to wait before abort (in microsecond, us). + @param Timeout Time to wait before abort (in millisecond, ms). @return EFI_SUCCESS The XHCI host controller is halt. @return EFI_TIMEOUT Failed to halt the XHCI before Timeout. @@ -553,7 +553,7 @@ XhcHaltHC ( Set the XHCI host controller to run. @param Xhc The XHCI Instance. - @param Timeout Time to wait before abort (in microsecond, us). + @param Timeout Time to wait before abort (in millisecond, ms). @return EFI_SUCCESS The XHCI host controller is running. @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout. diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h index 1a6256066599..0297072ffd6b 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h @@ -1,7 +1,7 @@ /** @file Private Header file for Usb Host Controller PEIM -Copyright (c) 2014, Intel Corporation. All rights reserved.
+Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions @@ -287,7 +287,7 @@ XhcPeiClearOpRegBit ( @param Offset The offset of the operational register. @param Bit The bit of the register to wait for. @param WaitToSet Wait the bit to set or clear. - @param Timeout The time to wait before abort (in microsecond, us). + @param Timeout The time to wait before abort (in millisecond, ms). @retval EFI_SUCCESS The bit successfully changed by host controller. @retval EFI_TIMEOUT The time out occurred. -- 2.7.0.windows.1