From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg0-x22d.google.com (mail-pg0-x22d.google.com [IPv6:2607:f8b0:400e:c05::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4EB6B21E1B75A for ; Thu, 21 Sep 2017 04:03:44 -0700 (PDT) Received: by mail-pg0-x22d.google.com with SMTP id c137so3327516pga.11 for ; Thu, 21 Sep 2017 04:06:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ZzSk4xB0R7zXN0UaAR2fAyjFC+Z156Cw6tzvcdAWaYw=; b=TV2eIy3kmlXL7HtqqK8tXUfSKhS7kRyiUMX3RjsPkXvud9QXyzNvsAKuUsY8R9+j9u T7SoxEjVodE4TMfqzhT3r4Px2SPr84eDDEnnFJVZfdv4yqHdPu+4uWGTRPGu5BiVkpqZ X8CqR9SXX0fhX1LyiZ4Tzw9DcXx/KYVjYiiQQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ZzSk4xB0R7zXN0UaAR2fAyjFC+Z156Cw6tzvcdAWaYw=; b=GiAfYE5ERHqwGedOhu4kLeoTYtH9iBOYvMgRlin+wc8+GHul9/rPuZkGBCWLNXJvXQ UykdjZGWHQkMinauwG+1oop9mtAr7zm5I+Afl6ToKrTu9098753nwtOSvvYFtr/S63bS If/m1ZnHR73sIT3sDpRQ3o7UA4K2Bmc7og/E+SMaBRG0SLMZfMu7t39vPYHtesyHnJpS 35Q/38ayf0mo3uq9IIf22EQmcwa/RaWMy9Oti1uA3utq1LXxafjv3p7B2pRrQuALMUUw 5mIgDfaEnlNjM7U/VOioeTo7rVKcz3CUC+J5IfrEK6UQer8LmcQWb4HtdrzNVKt2rOS2 Ay8Q== X-Gm-Message-State: AHPjjUhqud+0Xd7acJlkNOI54Flbq2eVHNeUVlnzYoaTod2Cms3eZY6B J8dqSYyLCE+5aNVUnEq+cOQihMrIUBw= X-Google-Smtp-Source: AOwi7QDW5gAikN66duPkjGrwdmDYcOL8Cif4Hriri+MqmcRmvaQRW1PtKILBnZ5+jv9lqNUBdb5phw== X-Received: by 10.98.27.210 with SMTP id b201mr5182832pfb.240.1505992010393; Thu, 21 Sep 2017 04:06:50 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id x124sm2090762pfx.56.2017.09.21.04.06.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Sep 2017 04:06:49 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, waip23@126.com, Heyi Guo Date: Thu, 21 Sep 2017 18:59:39 +0800 Message-Id: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 Subject: [PATCH edk2-platforms v3 00/11] Update D03/D05 binary for edk2 update and bug fix. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Sep 2017 11:03:44 -0000 Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: rp-1710-platforms-v3 rp-1710-osi-v3 Note: If occurs BIOS boot hang up issue, please revert below commit to fix: "2f03dc8" Chenhui Sun (1): Hisilicon/D03: Disable the function of PerfTuning Heyi Guo (4): Hisilicon/D05: Modify dsc and fdf file Hisilicon/D03: Modify dsc and fdf file Hisilicon: Fix the drivers use the same GUID issue Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase Ming Huang (4): Hisilicon D03/D05: get firmware version from FIRMWARE_VER D05/ACPI: Disable D05 SAS0 and SAS2 D05/ACPI: Modify I2C device Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device. huangming (2): Hisilicon/D05/Pcie: fix bug of size definition D05/PCIe: Modify PcieRegionBase of secondary chip Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf | 2 +- Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf | 2 +- Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf | 2 +- Platform/Hisilicon/D03/D03.dsc | 13 ++- Platform/Hisilicon/D03/D03.fdf | 5 +- Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 +- Platform/Hisilicon/D05/D05.dsc | 83 +++++++++-------- Platform/Hisilicon/D05/D05.fdf | 4 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 2 +- Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 2 +- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 38 ++++---- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++ Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 94 +++++++++++++++++++- Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 2 +- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 2 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +---- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 +++ Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 +- Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 2 +- 24 files changed, 205 insertions(+), 105 deletions(-) -- 1.9.1