public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: Heyi Guo <heyi.guo@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
	edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com,
	wanghuiqiang@huawei.com, huangming23@huawei.com,
	zhangjinsong2@huawei.com, waip23@126.com
Subject: [PATCH edk2-platforms v3 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip
Date: Thu, 21 Sep 2017 18:59:52 +0800	[thread overview]
Message-ID: <1505991597-52989-14-git-send-email-heyi.guo@linaro.org> (raw)
In-Reply-To: <1505991597-52989-1-git-send-email-heyi.guo@linaro.org>

From: huangming <huangming23@huawei.com>

On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are
0x20000000 and 0x30000000 based. These addresses overlap with the DDR
memory range 0-1G. In this situation, on the inbound direction, our pcie
will drop the DDR address access that are located in the pci range window
and lead to a dataflow error.

Modify 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses to 0x40000000
and decrease PciRegion Size accordingly.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
---
 Platform/Hisilicon/D05/D05.dsc                         | 12 ++++++------
 Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl |  8 ++++----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 01defe0..64101a7 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -329,12 +329,12 @@
   gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000
   gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
   gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000
-  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
-  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xb0000000
   gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
   gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000
-  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
-  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xb0000000
   gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
   gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000
   gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
@@ -352,9 +352,9 @@
   gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
   gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
   gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
-  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000
   gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
-  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000
   gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
   gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
   gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
index 79267e5..55c7f50 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
@@ -646,10 +646,10 @@ Scope(_SB)
           Cacheable,
           ReadWrite,
           0x0, // Granularity
-          0x20000000, // Min Base Address
+          0x40000000, // Min Base Address
           0xefffffff, // Max Base Address
           0x65000000000, // Translate
-          0xd0000000 // Length
+          0xb0000000 // Length
         )
         QWordIO (
           ResourceProducer,
@@ -766,10 +766,10 @@ Scope(_SB)
           Cacheable,
           ReadWrite,
           0x0, // Granularity
-          0x30000000, // Min Base Address
+          0x40000000, // Min Base Address
           0xefffffff, // Max Base Address
           0x75000000000, // Translate
-          0xc0000000 // Length
+          0xb0000000 // Length
         )
         QWordIO (
           ResourceProducer,
-- 
1.9.1



  parent reply	other threads:[~2017-09-21 11:04 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-21 10:59 [PATCH edk2-platforms v3 00/11] Update D03/D05 binary for edk2 update and bug fix Heyi Guo
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 1/7] Hisilicon/D03/Net: Update Snp driver Heyi Guo
2017-09-21 12:51   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 01/11] Hisilicon/D05: Modify dsc and fdf file Heyi Guo
2017-09-21 13:01   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 02/11] Hisilicon/D03: " Heyi Guo
2017-09-21 13:02   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 2/7] Hisilicon/D03/Sas: Add SasPlatform Heyi Guo
2017-09-21 12:49   ` Leif Lindholm
     [not found]     ` <3A622B96E322004395454DF73A38DDFA75577DB2@dggemm508-mbx.china.huawei.com>
2017-09-23 16:52       ` 答复: " Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 3/7] Hisilicon/D03: Update binary file Heyi Guo
2017-09-21 12:54   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 03/11] Hisilicon: Fix the drivers use the same GUID issue Heyi Guo
2017-09-21 10:59 ` [PATCH edk2-platforms v3 04/11] Hisilicon D03/D05: get firmware version from FIRMWARE_VER Heyi Guo
2017-09-21 13:03   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 4/7] Hisilicon/D05/Net: Update Snp driver Heyi Guo
2017-09-21 12:56   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 5/7] Hisilicon/D05/Sas: Add SasPlatform Heyi Guo
2017-09-21 13:00   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase Heyi Guo
2017-09-21 12:57   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 06/11] Hisilicon/D05/Pcie: fix bug of size definition Heyi Guo
2017-09-21 13:04   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 6/7] Hisilicon/D05: Update binary file Heyi Guo
2017-09-21 12:59   ` Leif Lindholm
     [not found]     ` <3A622B96E322004395454DF73A38DDFA75577D70@dggemm508-mbx.china.huawei.com>
2017-09-22  9:55       ` 答复: " Leif Lindholm
2017-09-21 10:59 ` Heyi Guo [this message]
2017-09-21 13:04   ` [PATCH edk2-platforms v3 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-non-osi v3 7/7] Hisilicon: Fix the drivers use the same GUID issue Heyi Guo
2017-09-21 10:59 ` [PATCH edk2-platforms v3 08/11] Hisilicon/D03: Disable the function of PerfTuning Heyi Guo
2017-09-21 13:07   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 09/11] D05/ACPI: Disable D05 SAS0 and SAS2 Heyi Guo
2017-09-21 13:11   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 10/11] D05/ACPI: Modify I2C device Heyi Guo
2017-09-21 13:12   ` Leif Lindholm
2017-09-21 10:59 ` [PATCH edk2-platforms v3 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device Heyi Guo
2017-09-21 13:14   ` Leif Lindholm
2017-09-21 12:11 ` [PATCH edk2-platforms v3 00/11] Update D03/D05 binary for edk2 update and bug fix graeme.gregory
2017-09-21 12:40 ` Leif Lindholm
2017-09-21 13:32   ` Ard Biesheuvel
2017-09-22  3:20     ` Heyi Guo

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1505991597-52989-14-git-send-email-heyi.guo@linaro.org \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox