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From: Jiewen Yao <jiewen.yao@intel.com>
To: edk2-devel@lists.01.org
Cc: Star Zeng <star.zeng@intel.com>
Subject: [PATCH 1/3] IntelSiliconPkg/VTdDxe: Clean up DXE flush memory.
Date: Fri, 22 Sep 2017 11:44:43 +0800	[thread overview]
Message-ID: <1506051885-21008-2-git-send-email-jiewen.yao@intel.com> (raw)
In-Reply-To: <1506051885-21008-1-git-send-email-jiewen.yao@intel.com>

Make sure the context table are flush to memory.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
---
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c   | 9 +++++++--
 IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 4 ++--
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
index ccecc95..cecb5d2 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c
@@ -124,7 +124,6 @@ CreateContextEntry (
       RootEntry->Bits.ContextTablePointerHi  = (UINT32) RShiftU64 ((UINT64)(UINTN)Buffer, 32);
       RootEntry->Bits.Present = 1;
       Buffer = (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages);
-      FlushPageTableMemory (VtdIndex, (UINTN)RootEntry, sizeof(*RootEntry));
     }
 
     ContextEntryTable = (VTD_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(RootEntry->Bits.ContextTablePointerLo, RootEntry->Bits.ContextTablePointerHi) ;
@@ -143,9 +142,10 @@ CreateContextEntry (
       ContextEntry->Bits.AddressWidth = 0x2;
       break;
     }
-    FlushPageTableMemory (VtdIndex, (UINTN)ContextEntry, sizeof(*ContextEntry));
   }
 
+  FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));
+
   return EFI_SUCCESS;
 }
 
@@ -196,6 +196,7 @@ CreateSecondLevelPagingEntryTable (
       DEBUG ((DEBUG_ERROR,"Could not Alloc LVL4 PT. \n"));
       return NULL;
     }
+    FlushPageTableMemory (VtdIndex, (UINTN)SecondLevelPagingEntry, EFI_PAGES_TO_SIZE(1));
   }
 
   //
@@ -219,6 +220,7 @@ CreateSecondLevelPagingEntryTable (
         ASSERT(FALSE);
         return NULL;
       }
+      FlushPageTableMemory (VtdIndex, (UINTN)Lvl4PtEntry[Index4].Uint64, SIZE_4KB);
       SetSecondLevelPagingEntryAttribute (&Lvl4PtEntry[Index4], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
     }
 
@@ -239,6 +241,7 @@ CreateSecondLevelPagingEntryTable (
           ASSERT(FALSE);
           return NULL;
         }
+        FlushPageTableMemory (VtdIndex, (UINTN)Lvl3PtEntry[Index3].Uint64, SIZE_4KB);
         SetSecondLevelPagingEntryAttribute (&Lvl3PtEntry[Index3], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
       }
 
@@ -542,6 +545,7 @@ GetSecondLevelPageTableEntry (
       *PageAttribute = PageNone;
       return NULL;
     }
+    FlushPageTableMemory (VtdIndex, (UINTN)L4PageTable[Index4], SIZE_4KB);
     SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&L4PageTable[Index4], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
     FlushPageTableMemory (VtdIndex, (UINTN)&L4PageTable[Index4], sizeof(L4PageTable[Index4]));
   }
@@ -555,6 +559,7 @@ GetSecondLevelPageTableEntry (
       *PageAttribute = PageNone;
       return NULL;
     }
+    FlushPageTableMemory (VtdIndex, (UINTN)L3PageTable[Index3], SIZE_4KB);
     SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&L3PageTable[Index3], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE);
     FlushPageTableMemory (VtdIndex, (UINTN)&L3PageTable[Index3], sizeof(L3PageTable[Index3]));
   }
diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
index 68b25a7..0b3006a 100644
--- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
+++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c
@@ -73,7 +73,6 @@ CreateExtContextEntry (
       ExtRootEntry->Bits.UpperContextTablePointerLo  = (UINT32) RShiftU64 ((UINT64)(UINTN)Buffer, 12) + 1;
       ExtRootEntry->Bits.UpperContextTablePointerHi  = (UINT32) RShiftU64 (RShiftU64 ((UINT64)(UINTN)Buffer, 12) + 1, 20);
       ExtRootEntry->Bits.UpperPresent = 1;
-      FlushPageTableMemory (VtdIndex, (UINTN)ExtRootEntry, sizeof(*ExtRootEntry));
       Buffer = (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages);
     }
 
@@ -93,9 +92,10 @@ CreateExtContextEntry (
       ExtContextEntry->Bits.AddressWidth = 0x2;
       break;
     }
-    FlushPageTableMemory (VtdIndex, (UINTN)ExtContextEntry, sizeof(*ExtContextEntry));
   }
 
+  FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages));
+
   return EFI_SUCCESS;
 }
 
-- 
2.7.4.windows.1



  reply	other threads:[~2017-09-22  3:41 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-22  3:44 [PATCH 0/3] IntelVTd fix Jiewen Yao
2017-09-22  3:44 ` Jiewen Yao [this message]
2017-09-22  3:44 ` [PATCH 2/3] IntelSiliconPkg/dec: Clarify VTdPolicy Jiewen Yao
2017-09-22  3:44 ` [PATCH 3/3] IntelSiliconPkg/VTdPmrPei: Add EndOfPei callback for S3 Jiewen Yao
2017-09-22  4:22   ` Zeng, Star
2017-09-22  4:42     ` Yao, Jiewen
2017-09-22  5:47       ` Zeng, Star

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