From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 165EF20945B6E for ; Thu, 21 Sep 2017 20:41:45 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2017 20:44:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,426,1500966000"; d="scan'208";a="1017219545" Received: from jyao1-mobl.ccr.corp.intel.com ([10.239.196.163]) by orsmga003.jf.intel.com with ESMTP; 21 Sep 2017 20:44:51 -0700 From: Jiewen Yao To: edk2-devel@lists.01.org Cc: Star Zeng Date: Fri, 22 Sep 2017 11:44:43 +0800 Message-Id: <1506051885-21008-2-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1506051885-21008-1-git-send-email-jiewen.yao@intel.com> References: <1506051885-21008-1-git-send-email-jiewen.yao@intel.com> Subject: [PATCH 1/3] IntelSiliconPkg/VTdDxe: Clean up DXE flush memory. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Sep 2017 03:41:45 -0000 Make sure the context table are flush to memory. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao --- IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c | 9 +++++++-- IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 4 ++-- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c index ccecc95..cecb5d2 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c @@ -124,7 +124,6 @@ CreateContextEntry ( RootEntry->Bits.ContextTablePointerHi = (UINT32) RShiftU64 ((UINT64)(UINTN)Buffer, 32); RootEntry->Bits.Present = 1; Buffer = (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages); - FlushPageTableMemory (VtdIndex, (UINTN)RootEntry, sizeof(*RootEntry)); } ContextEntryTable = (VTD_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(RootEntry->Bits.ContextTablePointerLo, RootEntry->Bits.ContextTablePointerHi) ; @@ -143,9 +142,10 @@ CreateContextEntry ( ContextEntry->Bits.AddressWidth = 0x2; break; } - FlushPageTableMemory (VtdIndex, (UINTN)ContextEntry, sizeof(*ContextEntry)); } + FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); + return EFI_SUCCESS; } @@ -196,6 +196,7 @@ CreateSecondLevelPagingEntryTable ( DEBUG ((DEBUG_ERROR,"Could not Alloc LVL4 PT. \n")); return NULL; } + FlushPageTableMemory (VtdIndex, (UINTN)SecondLevelPagingEntry, EFI_PAGES_TO_SIZE(1)); } // @@ -219,6 +220,7 @@ CreateSecondLevelPagingEntryTable ( ASSERT(FALSE); return NULL; } + FlushPageTableMemory (VtdIndex, (UINTN)Lvl4PtEntry[Index4].Uint64, SIZE_4KB); SetSecondLevelPagingEntryAttribute (&Lvl4PtEntry[Index4], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); } @@ -239,6 +241,7 @@ CreateSecondLevelPagingEntryTable ( ASSERT(FALSE); return NULL; } + FlushPageTableMemory (VtdIndex, (UINTN)Lvl3PtEntry[Index3].Uint64, SIZE_4KB); SetSecondLevelPagingEntryAttribute (&Lvl3PtEntry[Index3], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); } @@ -542,6 +545,7 @@ GetSecondLevelPageTableEntry ( *PageAttribute = PageNone; return NULL; } + FlushPageTableMemory (VtdIndex, (UINTN)L4PageTable[Index4], SIZE_4KB); SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&L4PageTable[Index4], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); FlushPageTableMemory (VtdIndex, (UINTN)&L4PageTable[Index4], sizeof(L4PageTable[Index4])); } @@ -555,6 +559,7 @@ GetSecondLevelPageTableEntry ( *PageAttribute = PageNone; return NULL; } + FlushPageTableMemory (VtdIndex, (UINTN)L3PageTable[Index3], SIZE_4KB); SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&L3PageTable[Index3], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); FlushPageTableMemory (VtdIndex, (UINTN)&L3PageTable[Index3], sizeof(L3PageTable[Index3])); } diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c index 68b25a7..0b3006a 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c @@ -73,7 +73,6 @@ CreateExtContextEntry ( ExtRootEntry->Bits.UpperContextTablePointerLo = (UINT32) RShiftU64 ((UINT64)(UINTN)Buffer, 12) + 1; ExtRootEntry->Bits.UpperContextTablePointerHi = (UINT32) RShiftU64 (RShiftU64 ((UINT64)(UINTN)Buffer, 12) + 1, 20); ExtRootEntry->Bits.UpperPresent = 1; - FlushPageTableMemory (VtdIndex, (UINTN)ExtRootEntry, sizeof(*ExtRootEntry)); Buffer = (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages); } @@ -93,9 +92,10 @@ CreateExtContextEntry ( ExtContextEntry->Bits.AddressWidth = 0x2; break; } - FlushPageTableMemory (VtdIndex, (UINTN)ExtContextEntry, sizeof(*ExtContextEntry)); } + FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); + return EFI_SUCCESS; } -- 2.7.4.windows.1