From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C277021F2AF7A for ; Thu, 28 Sep 2017 01:45:56 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP; 28 Sep 2017 01:49:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,449,1500966000"; d="scan'208";a="154297076" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.57]) by orsmga005.jf.intel.com with ESMTP; 28 Sep 2017 01:49:09 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Jiewen Yao , Ruiyu Ni Date: Thu, 28 Sep 2017 16:49:06 +0800 Message-Id: <1506588546-7636-1-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 Subject: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Combine INIT-SIPI-SIPI. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Sep 2017 08:45:57 -0000 In S3 resume path, current implementation do 2 separate INIT-SIPI-SIPI, this is not necessary. This change combine these 2 INIT-SIPI-SIPI to 1 and add CpuPause between them. Cc: Jiewen Yao Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 112 +++++++++++++++----------------------- 1 file changed, 44 insertions(+), 68 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c index 9404501..6dc4886 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -39,6 +39,11 @@ typedef struct { // SPIN_LOCK *mMemoryMappedLock = NULL; +// +// Signal that SMM BASE relocation is complete. +// +volatile BOOLEAN mInitApsAfterSmmBaseReloc; + /** Get starting address and size of the rendezvous entry for APs. Information for fixing a jump instruction in the code is also returned. @@ -343,62 +348,59 @@ SetProcessorRegister ( } /** - AP initialization before SMBASE relocation in the S3 boot path. + Set registers for the current processor. + + @param RegisterTableList The input registers list. + **/ VOID -EarlyMPRendezvousProcedure ( - VOID +SetRegisters ( + IN CPU_REGISTER_TABLE *RegisterTableList ) { - CPU_REGISTER_TABLE *RegisterTableList; UINT32 InitApicId; UINTN Index; - LoadMtrrData (mAcpiCpuData.MtrrTable); - - // - // Find processor number for this CPU. - // - RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable; InitApicId = GetInitialApicId (); for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { if (RegisterTableList[Index].InitialApicId == InitApicId) { SetProcessorRegister (&RegisterTableList[Index]); - break; + return; } } - - // - // Count down the number with lock mechanism. - // - InterlockedDecrement (&mNumberToFinish); } /** - AP initialization after SMBASE relocation in the S3 boot path. + AP initialization before then after SMBASE relocation in the S3 boot path. **/ VOID MPRendezvousProcedure ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; UINTN TopOfStack; UINT8 Stack[128]; + LoadMtrrData (mAcpiCpuData.MtrrTable); + + SetRegisters ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable); + + // + // Count down the number with lock mechanism. + // + InterlockedDecrement (&mNumberToFinish); + + // + // Wait for BSP to signal SMM Base relocation done. + // + while (!mInitApsAfterSmmBaseReloc) { + CpuPause (); + } + ProgramVirtualWireMode (); DisableLvtInterrupts (); - RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable; - InitApicId = GetInitialApicId (); - for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId == InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetRegisters ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable); // // Place AP into the safe code, count down the number with lock mechanism in the safe code. @@ -473,34 +475,25 @@ PrepareApStartupVector ( **/ VOID -EarlyInitializeCpu ( +InitializeCpuBeforeRebase ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - LoadMtrrData (mAcpiCpuData.MtrrTable); - // - // Find processor number for this CPU. - // - RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable; - InitApicId = GetInitialApicId (); - for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId == InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetRegisters ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable); ProgramVirtualWireMode (); PrepareApStartupVector (mAcpiCpuData.StartupVector); mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1; - mExchangeInfo->ApFunction = (VOID *) (UINTN) EarlyMPRendezvousProcedure; + mExchangeInfo->ApFunction = (VOID *) (UINTN) MPRendezvousProcedure; + + // + // Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots. + // + mInitApsAfterSmmBaseReloc = FALSE; // // Send INIT IPI - SIPI to all APs @@ -520,35 +513,18 @@ EarlyInitializeCpu ( **/ VOID -InitializeCpu ( +InitializeCpuAfterRebase ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - - RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable; - InitApicId = GetInitialApicId (); - for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId == InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetRegisters ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable); mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1; - // - // StackStart was updated when APs were waken up in EarlyInitializeCpu. - // Re-initialize StackAddress to original beginning address. - // - mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress; - mExchangeInfo->ApFunction = (VOID *) (UINTN) MPRendezvousProcedure; // - // Send INIT IPI - SIPI to all APs + // Signal that SMM base relocation is complete and to continue initialization. // - SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector); + mInitApsAfterSmmBaseReloc = TRUE; while (mNumberToFinish > 0) { CpuPause (); @@ -659,7 +635,7 @@ SmmRestoreCpu ( // // First time microcode load and restore MTRRs // - EarlyInitializeCpu (); + InitializeCpuBeforeRebase (); } // @@ -674,7 +650,7 @@ SmmRestoreCpu ( // // Restore MSRs for BSP and all APs // - InitializeCpu (); + InitializeCpuAfterRebase (); } // -- 2.7.0.windows.1