From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::235; helo=mail-pf0-x235.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x235.google.com (mail-pf0-x235.google.com [IPv6:2607:f8b0:400e:c00::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C863420945B68 for ; Thu, 28 Sep 2017 20:23:31 -0700 (PDT) Received: by mail-pf0-x235.google.com with SMTP id u12so61124pfl.4 for ; Thu, 28 Sep 2017 20:26:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=yN0+RRymIv4wTehCIUsweK6EdHy8GsWVeWIrew7KIWk=; b=Xo6Fqu4oGqoXexaBxfdqmHsQjSO4Hs6VMAvuZ8up8j3P0E13ZSw3ZNPb5rEu4bRLU9 4r9CEHTcTkgPAOoZSLRvLwUi0+vLbEB4eWH/Z0VFOsp05toflZh5J9oj9D0eJkaMOq++ El57wfmG866o+4kSM/hrBrWmYzcTmJ5bQpPzU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=yN0+RRymIv4wTehCIUsweK6EdHy8GsWVeWIrew7KIWk=; b=LNb9EEWbe9naUgcUux9x74N5tLL8AjHb8pYkYfRH1t6VCM5oWsg0IcCsMR3G2yiM3u GrWCRXn2XWwxymLcGHf8XYptD+qMHoTR6AEKfPitzdg5I8IGRU6ObCePgvHz423nGsF3 s5mUh3BHXvUqy/e/5gEraRGVbMqjLM16JbfxFmpklHu4a9YDfoe2MkPRD93uAODidkoe ocZXKQLc5wQgFMSYntC7qqKSnSmJLjhj1p7MtVcajee67KLbY2Dk6lzExN/cOrJbCqHb 2ZBuPumEOn1yPtKsmWuSQnrKUXpq09HkBx37Oa0ao8q23TVGWJ/IBmYG2DAF7gPzTjQZ kwjA== X-Gm-Message-State: AHPjjUgqiCegPAVxexmnayrmL1CpBd91CdNAdohCNFqGDUyI0HnQPH+0 JSECnNiM3rKs/ogS8ODexLhK8w== X-Google-Smtp-Source: AOwi7QC3YUy/uFieLqhjGkcSNMoEWdwQvaW9dzcxI9+RvFkzLLSr1CsmkVvVqStmEVwPrcDjSlIWbw== X-Received: by 10.98.67.134 with SMTP id l6mr6198499pfi.165.1506655606962; Thu, 28 Sep 2017 20:26:46 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.26.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:26:46 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, mengfanrong@huawei.com, waip23@126.com, Heyi Guo Date: Fri, 29 Sep 2017 11:19:39 +0800 Message-Id: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 Subject: [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Sep 2017 03:23:31 -0000 Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: rp-1710-platforms-v5 Note: 1. There may be some minor issue (or even in SoC IP) that causes D05/3 into exception, which was just found when we updated edk2 and edk2-platforms. We will continue to investigate the issue. It boot successfully by switch the VirtualEhciPciIo with old one. 2. The separate patch (Add AddressTranslationOffset support) is a prerequisite for this series and it's source can also be found in above branch(rp-1710-platforms-v5). Chenhui Sun (1): Hisilicon/D03: Disable the function of PerfTuning Heyi Guo (4): Hisilicon/D05: Modify dsc and fdf file Hisilicon/D03: Modify dsc and fdf file Hisilicon: Fix the drivers use the same GUID issue Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase Jason zhang (1): Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device. Ming Huang (5): Hisilicon D03/D05: get firmware version from FIRMWARE_VER Hisilicon/D05/Pcie: fix bug of size definition D05/PCIe: Modify PcieRegionBase of secondary chip D05/ACPI: Disable D05 SAS0 and SAS2 D05/ACPI: Modify I2C device Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf | 2 +- Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf | 2 +- Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf | 2 +- Platform/Hisilicon/D03/D03.dsc | 12 ++- Platform/Hisilicon/D03/D03.fdf | 4 +- Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 +- Platform/Hisilicon/D05/D05.dsc | 83 +++++++++-------- Platform/Hisilicon/D05/D05.fdf | 4 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 2 +- Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 2 +- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 38 ++++---- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++ Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 94 +++++++++++++++++++- Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 2 +- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 3 +- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 50 ----------- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +---- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 +++ Silicon/Hisilicon/HisiPkg.dec | 1 - Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 +- Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 2 +- 26 files changed, 203 insertions(+), 157 deletions(-) -- 1.9.1