From: Heyi Guo <heyi.guo@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com,
wanghuiqiang@huawei.com, huangming23@huawei.com,
zhangjinsong2@huawei.com, mengfanrong@huawei.com, waip23@126.com,
Heyi Guo <heyi.guo@linaro.org>
Subject: [PATCH edk2-platforms v5 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device.
Date: Fri, 29 Sep 2017 11:19:50 +0800 [thread overview]
Message-ID: <1506655190-56231-12-git-send-email-heyi.guo@linaro.org> (raw)
In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org>
From: Jason zhang <zhangjinsong2@huawei.com>
1. Because Hi161x chip doesn't support "ARI Forwarding Enable"
function, BIOS will enumerate 32 same devices (Device Number 0~31)
when a Non-ARI capable device attached in the RP. Hi161x chip will
not fix it, need BIOS patch.
2. Just enlarge iatu for those root port with ARI capable device
attached, Non-ARI capable device's RP, keep iatu limitation.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason zhang <zhangjinsong2@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 1 +
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 79 ++++++++++++++++++++
3 files changed, 87 insertions(+)
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
index e3d3988..9fa3f84 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
@@ -839,6 +839,7 @@ NotifyPhase(
case EfiPciHostBridgeEndEnumeration:
PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n");
+ EnlargeAtuConfig0 (This);
break;
case EfiPciHostBridgeBeginBusAllocation:
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h
index cddda6b..c04361f 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h
@@ -401,6 +401,9 @@ PreprocessController (
#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
+#define INVALID_CAPABILITY_00 0x00
+#define INVALID_CAPABILITY_FF 0xFF
+#define PCI_CAPABILITY_POINTER_MASK 0xFC
//
// Driver Instance Data Prototypes
@@ -518,4 +521,8 @@ RootBridgeConstructor (
IN UINT32 Seg
);
+VOID
+EnlargeAtuConfig0 (
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This
+ );
#endif
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index 10d766a..b57bd51 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -14,6 +14,7 @@
**/
#include "PciHostBridge.h"
+#include <IndustryStandard/PciExpress30.h>
#include <Library/DevicePathLib.h>
#include <Library/DmaLib.h>
#include <Library/PciExpressLib.h>
@@ -2322,3 +2323,81 @@ RootBridgeIoConfiguration (
return EFI_SUCCESS;
}
+BOOLEAN
+PcieCheckAriFwdEn (
+ UINTN PciBaseAddr
+ )
+{
+ UINT8 PciPrimaryStatus;
+ UINT8 CapabilityOffset;
+ UINT8 CapId;
+ UINT8 TempData;
+
+ PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET);
+
+ if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) {
+ CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET);
+ CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK;
+
+ while ((CapabilityOffset != INVALID_CAPABILITY_00) && (CapabilityOffset != INVALID_CAPABILITY_FF)) {
+ CapId = MmioRead8 (PciBaseAddr + CapabilityOffset);
+ if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) {
+ break;
+ }
+ CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1);
+ CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK;
+ }
+ } else {
+ PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__);
+ return FALSE;
+ }
+
+ if ((CapabilityOffset == INVALID_CAPABILITY_FF) || (CapabilityOffset == INVALID_CAPABILITY_00)) {
+ PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__);
+ return FALSE;
+ }
+
+ TempData = MmioRead16 (PciBaseAddr + CapabilityOffset +
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET);
+ TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING;
+
+ if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) {
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+}
+
+VOID
+EnlargeAtuConfig0 (
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This
+ )
+{
+ UINTN RbPciBase;
+ UINT64 MemLimit;
+ LIST_ENTRY *List;
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
+
+ PCIE_DEBUG ("In Enlarge RP iatu Config 0.\n");
+
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
+ List = HostBridgeInstance->Head.ForwardLink;
+
+ while (List != &HostBridgeInstance->Head) {
+ PCIE_DEBUG ("HostBridge has data.\n");
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
+
+ RbPciBase = RootBridgeInstance->RbPciBar;
+
+ // Those ARI FWD Enable Root Bridge, need enlarge iatu window.
+ if (PcieCheckAriFwdEn (RbPciBase)) {
+ MemLimit = GetPcieCfgAddress (RootBridgeInstance->Ecam,
+ RootBridgeInstance->BusBase + 2, 0, 0, 0)
+ - 1;
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
+ }
+ List = List->ForwardLink;
+ }
+}
--
1.9.1
next prev parent reply other threads:[~2017-09-29 3:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 01/11] Hisilicon/D05: Modify dsc and fdf file Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 02/11] Hisilicon/D03: " Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 03/11] Hisilicon: Fix the drivers use the same GUID issue Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 04/11] Hisilicon D03/D05: get firmware version from FIRMWARE_VER Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 06/11] Hisilicon/D05/Pcie: fix bug of size definition Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 08/11] Hisilicon/D03: Disable the function of PerfTuning Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 09/11] D05/ACPI: Disable D05 SAS0 and SAS2 Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 10/11] D05/ACPI: Modify I2C device Heyi Guo
2017-09-29 3:19 ` Heyi Guo [this message]
2017-09-29 19:19 ` [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
2017-10-05 12:54 ` Leif Lindholm
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