From: Heyi Guo <heyi.guo@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com,
wanghuiqiang@huawei.com, huangming23@huawei.com,
zhangjinsong2@huawei.com, mengfanrong@huawei.com, waip23@126.com,
Heyi Guo <heyi.guo@linaro.org>
Subject: [PATCH edk2-platforms v5 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase
Date: Fri, 29 Sep 2017 11:19:44 +0800 [thread overview]
Message-ID: <1506655190-56231-6-git-send-email-heyi.guo@linaro.org> (raw)
In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org>
Io BAR should be based IoBase and Mem BAR should be based PciRegionBase.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 37 ++++++++++++--------
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 ++++++--
2 files changed, 35 insertions(+), 17 deletions(-)
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
index a970da6..e3d3988 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c
@@ -1410,9 +1410,8 @@ SetResource(
Ptr->ResType = 1;
Ptr->GenFlag = 0;
Ptr->SpecificFlag = 0;
- /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
- Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
- (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+ /* PCIE Device Iobar address should be based on IoBase */
+ Ptr->AddrRangeMin = RootBridgeInstance->IoBase;
Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
@@ -1429,9 +1428,13 @@ SetResource(
Ptr->GenFlag = 0;
Ptr->SpecificFlag = 0;
Ptr->AddrSpaceGranularity = 32;
- /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
- Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
- (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+ /* PCIE device Bar should be based on PciRegionBase */
+ if (RootBridgeInstance->PciRegionBase > MAX_UINT32) {
+ DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n"));
+ return EFI_UNSUPPORTED;
+ }
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
+ RootBridgeInstance->PciRegionBase;
Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
@@ -1448,9 +1451,13 @@ SetResource(
Ptr->GenFlag = 0;
Ptr->SpecificFlag = 6;
Ptr->AddrSpaceGranularity = 32;
- /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
- Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
- (RootBridgeInstance->MemBase & 0xFFFFFFFF);
+ /* PCIE device Bar should be based on PciRegionBase */
+ if (RootBridgeInstance->PciRegionBase > MAX_UINT32) {
+ DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n"));
+ return EFI_UNSUPPORTED;
+ }
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
+ RootBridgeInstance->PciRegionBase;
Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
@@ -1467,9 +1474,9 @@ SetResource(
Ptr->GenFlag = 0;
Ptr->SpecificFlag = 0;
Ptr->AddrSpaceGranularity = 64;
- /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
- Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
- (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
+ /* PCIE device Bar should be based on PciRegionBase */
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
+ RootBridgeInstance->PciRegionBase;
Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
@@ -1486,9 +1493,9 @@ SetResource(
Ptr->GenFlag = 0;
Ptr->SpecificFlag = 6;
Ptr->AddrSpaceGranularity = 64;
- /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
- Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
- (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
+ /* PCIE device Bar should be based on PciRegionBase */
+ Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase +
+ RootBridgeInstance->PciRegionBase;
Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index 03edcf1..10d766a 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -2301,8 +2301,19 @@ RootBridgeIoConfiguration (
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
for (Index = 0; Index < TypeMax; Index++) {
if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
- Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
- Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;
+ switch (Index) {
+ case TypeIo:
+ Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->IoBase;
+ break;
+ case TypeBus:
+ Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
+ break;
+ default:
+ /* PCIE Device bar address should be base on PciRegionBase */
+ Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base - PrivateData->MemBase +
+ PrivateData->PciRegionBase;
+ }
+ Configuration.SpaceDesp[Index].AddrRangeMax = Configuration.SpaceDesp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1;
Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;
}
}
--
1.9.1
next prev parent reply other threads:[~2017-09-29 3:23 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-29 3:19 [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 01/11] Hisilicon/D05: Modify dsc and fdf file Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 02/11] Hisilicon/D03: " Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 03/11] Hisilicon: Fix the drivers use the same GUID issue Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 04/11] Hisilicon D03/D05: get firmware version from FIRMWARE_VER Heyi Guo
2017-09-29 3:19 ` Heyi Guo [this message]
2017-09-29 3:19 ` [PATCH edk2-platforms v5 06/11] Hisilicon/D05/Pcie: fix bug of size definition Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 08/11] Hisilicon/D03: Disable the function of PerfTuning Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 09/11] D05/ACPI: Disable D05 SAS0 and SAS2 Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 10/11] D05/ACPI: Modify I2C device Heyi Guo
2017-09-29 3:19 ` [PATCH edk2-platforms v5 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device Heyi Guo
2017-09-29 19:19 ` [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix Heyi Guo
2017-10-05 12:54 ` Leif Lindholm
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