From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::229; helo=mail-pf0-x229.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x229.google.com (mail-pf0-x229.google.com [IPv6:2607:f8b0:400e:c00::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CC76720945B68 for ; Thu, 28 Sep 2017 20:23:54 -0700 (PDT) Received: by mail-pf0-x229.google.com with SMTP id d187so54313pfg.11 for ; Thu, 28 Sep 2017 20:27:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=axAqhG06bhdicOPruvqAk8NM/FW/iZgSUPSvmGntTrM=; b=Z/eK1ta0ktS3PNG4wd8mB4Ybks9LmoCTCOVfHj965o+/jhNjOxTfGigEAHKzNmM/bB KmaDT67le6CUYjRA1VdWql5eJS9x9TTMWMcKWuWhZ2dgogbdtejYMKGL44FemqTzzwm4 PZuYxlPYmqp+UVn//+BGFvH7WdPUxDuegJBV4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=axAqhG06bhdicOPruvqAk8NM/FW/iZgSUPSvmGntTrM=; b=gDTCYKPzL6LTRR6FJH6TlZs1Ks8vKq6ijQKblMRmAHcUXRjYClf9lu39LObPwJT/1B GIgiESdVid8bH03F6DnYjHI8ddZd1gMy+BYSg/ZWyQWRvhGREs/CVCg6B/Mh36TzjDO8 K7+SVSEhN5uWW11NvZuU2HXISzvVE7MUTxT/TX8PA9B3iF1aoWp1TQ5LrEaevOQnGc3v yfsOe/slRo7z5MN7uOHLkwNpLvKqGe+2EGIXh/rDEtHc2Sz7B18yt+2m9kGhlOmF/2k9 gK9Pa12bewqoL8vpsFLMb4lOAQ6FtEKz3/d3T8G6yv8yn1RGjddRxpldabwzteDAmjKg wV+A== X-Gm-Message-State: AHPjjUjxK+lCC2jv2R1d3E1EJbg1/lVCVHlTAy8sIA8IKlVnTbqvujhm eLUS309BYdkSeRqHKDxA8oufnA== X-Google-Smtp-Source: AOwi7QCsVZEuukZLYtnJLIME9Kz2A15Laot6mXLwFZ3FaYGDLQp0ssFQTTFytM/MMMtNqEON+sBMMA== X-Received: by 10.99.56.78 with SMTP id h14mr6039582pgn.192.1506655629864; Thu, 28 Sep 2017 20:27:09 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.27.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:27:09 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, mengfanrong@huawei.com, waip23@126.com, Chenhui Sun , Heyi Guo Date: Fri, 29 Sep 2017 11:19:47 +0800 Message-Id: <1506655190-56231-9-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [PATCH edk2-platforms v5 08/11] Hisilicon/D03: Disable the function of PerfTuning X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Sep 2017 03:23:54 -0000 From: Chenhui Sun The PerTuning function is not stable, it will cause the LSI SAS 3008/3108 crash, disable this function first. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo --- Platform/Hisilicon/D03/D03.dsc | 1 - Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 1 - Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 50 -------------------- Silicon/Hisilicon/HisiPkg.dec | 1 - 4 files changed, 53 deletions(-) diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index fca6781..f2a120e 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -112,7 +112,6 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE - gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE [PcdsFixedAtBuild.common] gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D03" diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index ee9dbed..61b091f 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -55,7 +55,6 @@ [FeaturePcd] gHisiTokenSpaceGuid.PcdIsItsSupported - gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable [depex] TRUE diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 8ab7fa3..f420c91 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -315,50 +315,6 @@ PcieEnableItssm ( } -STATIC EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - UINT32 Value; - UINTN RegSegmentOffset; - - if (Port >= PCIE_MAX_ROOTBRIDGE) { - DEBUG((DEBUG_ERROR, "Invalid port number: %d\n", Port)); - return EFI_INVALID_PARAMETER; - } - - RegSegmentOffset = PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET; - - //Enable SMMU bypass for translation - RegRead(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); - //BIT13: controller master read SMMU bypass - //BIT12: controller master write SMMU bypass - //BIT10: SMMU bypass enable - Value |= (BIT13 | BIT12 | BIT10); - RegWrite(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); - - //Switch strongly order (SO) to relaxed order (RO) for write transaction - RegRead(RegSegmentOffset + PCIE_CTRL_6_REG, Value); - //BIT13 | BIT12: Enable write merge and SMMU streaming ordered write acknowledge - Value |= (BIT13 | BIT12); - //BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17: Enable RO for all types of write transaction - Value |= (BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17); - RegWrite(RegSegmentOffset + PCIE_CTRL_6_REG, Value); - - //Force streamID for controller read operation - RegRead(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); - //Force using streamID in PCIE_SYS_CTRL54_REG - Value &= ~(BIT30); - //Set streamID to 0, bit[0:15] is for request ID and should be kept - Value &= ~(0xff << 16); - RegWrite(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); - - //Enable read and write snoopy - RegRead(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); - Value |= (BIT30 | BIT28); - RegWrite(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); - - return EFI_SUCCESS; -} - EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { PCIE_CTRL_7_U pcie_ctrl7; @@ -1141,12 +1097,6 @@ PciePortInit ( DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); /* assert LTSSM enable */ (VOID)PcieEnableItssm (soctype, HostBridgeNum, PortIndex, PcieCfg); - if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) { - //PCIe will still work even if performance tuning fails, - //and there is warning message inside the function to print - //detailed error if there is. - (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex); - } PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex); /* diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec index 2c02e14..81ba3be 100644 --- a/Silicon/Hisilicon/HisiPkg.dec +++ b/Silicon/Hisilicon/HisiPkg.dec @@ -274,7 +274,6 @@ [PcdsFeatureFlag] gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065 - gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066 -- 1.9.1