From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22c; helo=mail-lf0-x22c.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x22c.google.com (mail-lf0-x22c.google.com [IPv6:2a00:1450:4010:c07::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 087FB21EA15CC for ; Mon, 9 Oct 2017 09:50:43 -0700 (PDT) Received: by mail-lf0-x22c.google.com with SMTP id 90so19857290lfs.13 for ; Mon, 09 Oct 2017 09:54:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=O/et75SsDvULATOnbKgNnRKp0FPqFVB1FaxdMoiwZh4=; b=PBT1rN40ljSTgxnq4iwO2ae6VKbqsZUhI+wNffcSsnQkDEukLPZ61d4RJsuWNAB2d8 wcrOqA3HiE3zWKL5MJd8TF/HYb5a+eW1vgpItvV74sLpQYnskuNPROGfrdyCI8VXc4fK pvEeHvqWqbmb88qamXHZGX0zwjyj9VTRO80CdLAkaKDEl/Skhmxz+Pgwnccs0fD3RK10 KoZgZQ3QM+uAWN7/AVhXQxVscdWj+O6R7wBNdSqkQklX6Udd1DOe5wYEPV7sZbYisruw mnmHuIhowygWed+w9xmuu4SbAJJ0Y6+Gei7Jua6zuVWEjuD7yOZBiMVNqLOeorE4gZvv kUMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=O/et75SsDvULATOnbKgNnRKp0FPqFVB1FaxdMoiwZh4=; b=iHkuc0QjjRmOE8O4PSNtTbp+xk+Sx0Fn+4wb6KJ39nbC3ZsuK8iUUaI7YXNcA/KBx7 W3N01x4gbY0me3RqbL2G4zsxxvJstMCLgR4IcoWvA7xhykXMezkPblyoevKjWL0USLua zi893GLrcIBJLZDYNGKWINhXomIM8RtxXVe0RP3JqB2+G4B/QS2+md9hZ/m6RVC6dRwi eVwoasGjoPCRjpb+sXAAVcSAMxH7UVmJLl1NzfWaopPeVevgf0GOwDDj8sgqDi07sp6/ 5sLgsQFNc+sm2t3sI3TP+OTEovFPV5omeHi7MJmCmlPd/ImEW79qq5OEqclkc2dClr52 sxrg== X-Gm-Message-State: AMCzsaVY1oYg6bgO7E8dEnapWL/xCdde0v31xDxEa5lnxegN7TlCqjD3 u2OhKu6kfDFcB3XbmBmeMVlGkRcl7bE= X-Google-Smtp-Source: AOwi7QDN8hVR4EpDJRQ7tnB8hq68iEcB82NXgTom0alMHuIWP1m/OwX7Z/8QvwnR9K1BmOmZy8KLgQ== X-Received: by 10.46.67.156 with SMTP id z28mr5783804lje.124.1507568048447; Mon, 09 Oct 2017 09:54:08 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id z204sm1421490lff.33.2017.10.09.09.54.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 09:54:07 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com Date: Mon, 9 Oct 2017 19:00:53 +0200 Message-Id: <1507568462-28775-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507568462-28775-1-git-send-email-mw@semihalf.com> References: <1507568462-28775-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH 04/13] Marvell/Armada: Armada70x0Lib: Clean FV in the D-cache before boot X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Oct 2017 16:50:43 -0000 From: Ard Biesheuvel To prevent cache coherency issues when chainloading via U-Boot, clean and invalidate the FV image in the caches before re-enabling the MMU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S | 15 +++++++++++++++ Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 3 +++ 2 files changed, 18 insertions(+) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S index 72f8cfc..7544361 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S @@ -17,6 +17,21 @@ ASM_FUNC(ArmPlatformPeiBootAction) mov x29, xzr + + MOV32 (x0, FixedPcdGet64 (PcdFvBaseAddress)) + MOV32 (x3, FixedPcdGet32 (PcdFvSize)) + add x3, x3, x0 + + mrs x1, ctr_el0 + and x1, x1, #0xf // Dminline + mov x2, #4 + lsl x1, x2, x1 // by-VA stride for D-cache maintenance + +0:dc civac, x0 + add x0, x0, x1 + cmp x0, x3 + b.lt 0b + ret //UINTN diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf index 2e198c3..6966683 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -67,5 +67,8 @@ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdFvSize + [Ppis] gArmMpCoreInfoPpiGuid -- 1.8.3.1