From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22b; helo=mail-lf0-x22b.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x22b.google.com (mail-lf0-x22b.google.com [IPv6:2a00:1450:4010:c07::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6857E21EA15DA for ; Wed, 11 Oct 2017 03:12:40 -0700 (PDT) Received: by mail-lf0-x22b.google.com with SMTP id n69so1496620lfn.2 for ; Wed, 11 Oct 2017 03:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TtztnqOEA+dqX1b9tOWUSOVeM+ZgsPTKBfHC+zwyRTs=; b=LcHESo4UO02gTdv7/0KXMVloz4s7svt5Oni6UnWluj+Jih7qR2+HfxrSa0gZlWDl+u imB8vHAIF0ZsDu/+/bkuXmEhBey0qLW+AaN6mWUHD9DgTYK7VRwiYmj3RN/jlQdL0wgI Hpzl56SfSgrGjeYY3T7yi96tXj7Cf7NsvztR97oo3FitWJzqTobAKA5PXn++pOqFBkBV L7H73nblpDWKw+CpKU9BI2sZJgVZlWl/Cv0YRfm8V34dW+ozseTTvJOSCWlHbO/Eh1sK YYk91f2Bvt96BQoZlPjq9xACFvSdG5oCS06mK5IyutQKmHvOBPVoxFpGSTpJoUNU+35d 6hfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TtztnqOEA+dqX1b9tOWUSOVeM+ZgsPTKBfHC+zwyRTs=; b=UrOKxpDhKmyszbTXChC32AVlUMFqLRyvEsDbPLePPiLLRFNZq5DEIpRQMwJvnMOTOP yx1WR+zhwpR3Cb2mSIkrUqKvF7oTckUTf1nRvqxjYAFkc/s5xf2iQoNe5AyNb065EF46 Kc2Xztr/trMAxd6YEm4rdxvJKaPPWCtL/5wnA6YwwMLDHl1e2DtPPjeCRcB05SowV1jj coktMvilVu5RU1C87lrgG+3N3lszSTgdt5smHG7cDkqDFs2nCAIL/aXrjgTUVuVfBRW/ OKfKkF5Cx9apIkmU8X7LUuMZWD1M3FhADa5OacAj7si0stEXvWJ8Y19042Wicm6MgZ/U ZyWg== X-Gm-Message-State: AMCzsaVdloD4WCXEL5eh18c/V6VktJnAeBdWpJVB78rCBc4P+1oTCvrQ oHL2EUL01jTg3JpjvowBU3SSSTJEgFg= X-Google-Smtp-Source: AOwi7QBCci67uWsO99V00Gm9Y6nAuWrcvwdszkcWqQetl/yzuunc5v5GZ2AWgMidozx1ZCP30X1zqg== X-Received: by 10.25.145.88 with SMTP id y24mr3045651lfj.5.1507716967738; Wed, 11 Oct 2017 03:16:07 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.16.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:16:07 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com Date: Wed, 11 Oct 2017 12:15:34 +0200 Message-Id: <1507716939-31798-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v2 07/12] Marvell/Armada: Ensure GICC frames adjacency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Oct 2017 10:12:40 -0000 From: Ard Biesheuvel The GIC architecture mandates that the CPU interface, which consists of 2 consecutive 4 KB frames, can be mapped using separate mappings. Since this is problematic on 64 KB pages, the MMU-400 aliases each frame 16 times, and the two consecutive frames can be found at offset 0xf000. Therefore use the last alias from the first series of aliases as the base address, so that the first frame from the second series becomes directly adjacent, whilst remaining covered by a separate 64KB page. This patch is intended to expose correct GICC alias via MADT, once ACPI support is added. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc index 5071bd5..bd2336f 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -263,7 +263,14 @@ # ARM Generic Interrupt Controller gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF0220000 + + # + # NOTE: the GIC architecture mandates that the CPU interface, which consists + # of 2 consecutive 4 KB frames, can be mapped using separate mappings. + # Since this is problematic on 64 KB pages, the MMU-400 aliases each frame + # 16 times, and the two consecutive frames can be found at offset 0xf000 + # + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF022F000 # ARM Architectural Timer Support gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|25000000 -- 2.7.4