* [platforms: PATCH v2 1/8] Marvell/Armada: Implement EFI_RNG_PROTOCOL driver for EIP76 TRNG
2017-10-25 6:45 [platforms: PATCH v2 0/8] Armada 7k/8k - memory improvements Marcin Wojtas
@ 2017-10-25 6:45 ` Marcin Wojtas
2017-10-25 10:44 ` Leif Lindholm
2017-10-25 6:45 ` [platforms: PATCH v2 2/8] Marvell/Armada: Increase preallocated memory region size Marcin Wojtas
` (6 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Marcin Wojtas @ 2017-10-25 6:45 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, ard.biesheuvel, nadavh, neta, kostap, jinghua, mw,
jsd
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Add an implementation of EFI_RNG_PROTOCOL so that the OS loader has
access to entropy for KASLR and other purposes (i.e., seeding the OS's
entropy pool very early on).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Armada/Armada.dsc.inc | 4 +
Platform/Marvell/Armada/Armada70x0.fdf | 1 +
Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c | 255 ++++++++++++++++++++
Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf | 47 ++++
Platform/Marvell/Marvell.dec | 3 +
5 files changed, 310 insertions(+)
diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index 1aa485c..ec24d76 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -364,6 +364,9 @@
gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
gArmTokenSpaceGuid.PcdArmScr|0x531
+ # TRNG
+ gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
@@ -400,6 +403,7 @@
Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf
Platform/Marvell/Drivers/Spi/MvSpiDxe.inf
Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf
+ Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf
# Network support
MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
index 933c3ed..a94a9ff 100644
--- a/Platform/Marvell/Armada/Armada70x0.fdf
+++ b/Platform/Marvell/Armada/Armada70x0.fdf
@@ -113,6 +113,7 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
INF Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf
INF Platform/Marvell/Drivers/Spi/MvSpiDxe.inf
INF Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf
+ INF Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf
# Network support
INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c
new file mode 100644
index 0000000..014443d
--- /dev/null
+++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c
@@ -0,0 +1,255 @@
+/** @file
+
+ This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TRNG
+
+ Copyright (C) 2017, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/Rng.h>
+
+#define TRNG_OUTPUT_REG mTrngBaseAddress
+#define TRNG_OUTPUT_SIZE 0x10
+
+#define TRNG_STATUS_REG (mTrngBaseAddress + 0x10)
+#define TRNG_STATUS_READY BIT0
+
+#define TRNG_INTACK_REG (mTrngBaseAddress + 0x10)
+#define TRNG_INTACK_READY BIT0
+
+#define TRNG_CONTROL_REG (mTrngBaseAddress + 0x14)
+#define TRNG_CONTROL_REG_ENABLE BIT10
+
+#define TRNG_CONFIG_REG (mTrngBaseAddress + 0x18)
+#define __MIN_REFILL_SHIFT 0
+#define __MAX_REFILL_SHIFT 16
+#define TRNG_CONFIG_MIN_REFILL_CYCLES (0x05 << __MIN_REFILL_SHIFT)
+#define TRNG_CONFIG_MAX_REFILL_CYCLES (0x22 << __MAX_REFILL_SHIFT)
+
+#define TRNG_FRODETUNE_REG (mTrngBaseAddress + 0x24)
+#define TRNG_FRODETUNE_MASK 0x0
+
+#define TRNG_FROENABLE_REG (mTrngBaseAddress + 0x20)
+#define TRNG_FROENABLE_MASK 0xffffff
+
+#define TRNG_MAX_RETRIES 20
+
+STATIC EFI_PHYSICAL_ADDRESS mTrngBaseAddress;
+
+/**
+ Returns information about the random number generation implementation.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL
+ instance.
+ @param[in,out] RNGAlgorithmListSize On input, the size in bytes of
+ RNGAlgorithmList.
+ On output with a return code of
+ EFI_SUCCESS, the size in bytes of the
+ data returned in RNGAlgorithmList. On
+ output with a return code of
+ EFI_BUFFER_TOO_SMALL, the size of
+ RNGAlgorithmList required to obtain the
+ list.
+ @param[out] RNGAlgorithmList A caller-allocated memory buffer filled
+ by the driver with one EFI_RNG_ALGORITHM
+ element for each supported RNG algorithm.
+ The list must not change across multiple
+ calls to the same driver. The first
+ algorithm in the list is the default
+ algorithm for the driver.
+
+ @retval EFI_SUCCESS The RNG algorithm list was returned
+ successfully.
+ @retval EFI_UNSUPPORTED The services is not supported by this
+ driver.
+ @retval EFI_DEVICE_ERROR The list of algorithms could not be
+ retrieved due to a hardware or firmware
+ error.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are
+ incorrect.
+ @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small
+ to hold the result.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+Armada70x0RngGetInfo (
+ IN EFI_RNG_PROTOCOL *This,
+ IN OUT UINTN *RNGAlgorithmListSize,
+ OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
+ )
+{
+ if (This == NULL || RNGAlgorithmListSize == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (*RNGAlgorithmListSize < sizeof (EFI_RNG_ALGORITHM)) {
+ *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ if (RNGAlgorithmList == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
+ CopyGuid (RNGAlgorithmList, &gEfiRngAlgorithmRaw);
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+GetTrngData (
+ IN UINTN Length,
+ OUT UINT8 *Bits
+ )
+{
+ UINTN Tries;
+ UINT32 Buf[TRNG_OUTPUT_SIZE / sizeof (UINT32)];
+ UINTN Index;
+
+ for (Tries = 0; Tries < TRNG_MAX_RETRIES; Tries++) {
+ if (MmioRead32 (TRNG_STATUS_REG) & TRNG_STATUS_READY) {
+ for (Index = 0; Index < ARRAY_SIZE (Buf); Index++) {
+ Buf[Index] = MmioRead32 (TRNG_OUTPUT_REG + Index * sizeof (UINT32));
+ }
+ CopyMem (Bits, Buf, Length);
+ MmioWrite32 (TRNG_INTACK_REG, TRNG_INTACK_READY);
+
+ return EFI_SUCCESS;
+ }
+ // Wait for more TRNG data to arrive
+ gBS->Stall (10);
+ }
+ return EFI_DEVICE_ERROR;
+}
+
+/**
+ Produces and returns an RNG value using either the default or specified RNG
+ algorithm.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL
+ instance.
+ @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that
+ identifies the RNG algorithm to use. May
+ be NULL in which case the function will
+ use its default RNG algorithm.
+ @param[in] RNGValueLength The length in bytes of the memory buffer
+ pointed to by RNGValue. The driver shall
+ return exactly this numbers of bytes.
+ @param[out] RNGValue A caller-allocated memory buffer filled
+ by the driver with the resulting RNG
+ value.
+
+ @retval EFI_SUCCESS The RNG value was returned successfully.
+ @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm
+ is not supported by this driver.
+ @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due
+ to a hardware or firmware error.
+ @retval EFI_NOT_READY There is not enough random data available
+ to satisfy the length requested by
+ RNGValueLength.
+ @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is
+ zero.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+Armada70x0RngGetRNG (
+ IN EFI_RNG_PROTOCOL *This,
+ IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL
+ IN UINTN RNGValueLength,
+ OUT UINT8 *RNGValue
+ )
+{
+ UINTN Length;
+ EFI_STATUS Status;
+
+ if (This == NULL || RNGValueLength == 0 || RNGValue == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // We only support the raw algorithm, so reject requests for anything else
+ //
+ if (RNGAlgorithm != NULL &&
+ !CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ do {
+ Length = MIN (RNGValueLength, TRNG_OUTPUT_SIZE);
+ Status = GetTrngData (Length, RNGValue);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ RNGValue += Length;
+ RNGValueLength -= Length;
+ } while (RNGValueLength > 0);
+
+ return EFI_SUCCESS;
+}
+
+STATIC EFI_RNG_PROTOCOL mArmada70x0RngProtocol = {
+ Armada70x0RngGetInfo,
+ Armada70x0RngGetRNG
+};
+
+//
+// Entry point of this driver.
+//
+EFI_STATUS
+EFIAPI
+Armada70x0RngDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ mTrngBaseAddress = PcdGet64 (PcdEip76TrngBaseAddress);
+
+ //
+ // Disable the TRNG before updating its configuration
+ //
+ MmioAnd32 (TRNG_CONTROL_REG, ~TRNG_CONTROL_REG_ENABLE);
+
+ //
+ // Configure the internal conditioning parameters of the TRNG
+ //
+ MmioWrite32 (TRNG_CONFIG_REG, TRNG_CONFIG_MIN_REFILL_CYCLES |
+ TRNG_CONFIG_MAX_REFILL_CYCLES);
+
+ //
+ // Configure the FROs
+ //
+ MmioWrite32 (TRNG_FRODETUNE_REG, TRNG_FRODETUNE_MASK);
+ MmioWrite32 (TRNG_FROENABLE_REG, TRNG_FROENABLE_MASK);
+
+ //
+ // Enable the TRNG
+ //
+ MmioOr32 (TRNG_CONTROL_REG, TRNG_CONTROL_REG_ENABLE);
+
+ return SystemTable->BootServices->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gEfiRngProtocolGuid,
+ &mArmada70x0RngProtocol,
+ NULL
+ );
+}
diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf
new file mode 100644
index 0000000..189ffc5
--- /dev/null
+++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf
@@ -0,0 +1,47 @@
+## @file
+# This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TRNG
+#
+# Copyright (C) 2017, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = Armada70x0RngDxe
+ FILE_GUID = dd87096a-cae5-4328-bec1-2ddb755f2e08
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = Armada70x0RngDxeEntryPoint
+
+[Sources]
+ Armada70x0RngDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/Marvell/Marvell.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ IoLib
+ PcdLib
+ UefiDriverEntryPoint
+
+[Pcd]
+ gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress
+
+[Protocols]
+ gEfiRngProtocolGuid ## PRODUCES
+
+[Guids]
+ gEfiRngAlgorithmRaw
+
+[Depex]
+ TRUE
diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
index e7d7c2c..78f5e53 100644
--- a/Platform/Marvell/Marvell.dec
+++ b/Platform/Marvell/Marvell.dec
@@ -195,6 +195,9 @@
#RTC
gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052
+#TRNG
+ gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053
+
[Protocols]
gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}
gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }}
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [platforms: PATCH v2 1/8] Marvell/Armada: Implement EFI_RNG_PROTOCOL driver for EIP76 TRNG
2017-10-25 6:45 ` [platforms: PATCH v2 1/8] Marvell/Armada: Implement EFI_RNG_PROTOCOL driver for EIP76 TRNG Marcin Wojtas
@ 2017-10-25 10:44 ` Leif Lindholm
0 siblings, 0 replies; 12+ messages in thread
From: Leif Lindholm @ 2017-10-25 10:44 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel, ard.biesheuvel, nadavh, neta, kostap, jinghua, jsd
On Wed, Oct 25, 2017 at 08:45:23AM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> Add an implementation of EFI_RNG_PROTOCOL so that the OS loader has
> access to entropy for KASLR and other purposes (i.e., seeding the OS's
> entropy pool very early on).
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/Marvell/Armada/Armada.dsc.inc | 4 +
> Platform/Marvell/Armada/Armada70x0.fdf | 1 +
> Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c | 255 ++++++++++++++++++++
> Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf | 47 ++++
> Platform/Marvell/Marvell.dec | 3 +
> 5 files changed, 310 insertions(+)
>
> diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
> index 1aa485c..ec24d76 100644
> --- a/Platform/Marvell/Armada/Armada.dsc.inc
> +++ b/Platform/Marvell/Armada/Armada.dsc.inc
> @@ -364,6 +364,9 @@
> gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
> gArmTokenSpaceGuid.PcdArmScr|0x531
>
> + # TRNG
> + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000
> +
> ################################################################################
> #
> # Components Section - list of all EDK II Modules needed by this Platform
> @@ -400,6 +403,7 @@
> Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf
> Platform/Marvell/Drivers/Spi/MvSpiDxe.inf
> Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf
> + Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf
>
> # Network support
> MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
> index 933c3ed..a94a9ff 100644
> --- a/Platform/Marvell/Armada/Armada70x0.fdf
> +++ b/Platform/Marvell/Armada/Armada70x0.fdf
> @@ -113,6 +113,7 @@ FvNameGuid = 5eda4200-2c5f-43cb-9da3-0baf74b1b30c
> INF Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf
> INF Platform/Marvell/Drivers/Spi/MvSpiDxe.inf
> INF Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf
> + INF Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf
>
> # Network support
> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c
> new file mode 100644
> index 0000000..014443d
> --- /dev/null
> +++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c
> @@ -0,0 +1,255 @@
> +/** @file
> +
> + This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TRNG
> +
> + Copyright (C) 2017, Linaro Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +#include <Protocol/Rng.h>
> +
> +#define TRNG_OUTPUT_REG mTrngBaseAddress
> +#define TRNG_OUTPUT_SIZE 0x10
> +
> +#define TRNG_STATUS_REG (mTrngBaseAddress + 0x10)
> +#define TRNG_STATUS_READY BIT0
> +
> +#define TRNG_INTACK_REG (mTrngBaseAddress + 0x10)
> +#define TRNG_INTACK_READY BIT0
> +
> +#define TRNG_CONTROL_REG (mTrngBaseAddress + 0x14)
> +#define TRNG_CONTROL_REG_ENABLE BIT10
> +
> +#define TRNG_CONFIG_REG (mTrngBaseAddress + 0x18)
> +#define __MIN_REFILL_SHIFT 0
> +#define __MAX_REFILL_SHIFT 16
> +#define TRNG_CONFIG_MIN_REFILL_CYCLES (0x05 << __MIN_REFILL_SHIFT)
> +#define TRNG_CONFIG_MAX_REFILL_CYCLES (0x22 << __MAX_REFILL_SHIFT)
> +
> +#define TRNG_FRODETUNE_REG (mTrngBaseAddress + 0x24)
> +#define TRNG_FRODETUNE_MASK 0x0
> +
> +#define TRNG_FROENABLE_REG (mTrngBaseAddress + 0x20)
> +#define TRNG_FROENABLE_MASK 0xffffff
> +
> +#define TRNG_MAX_RETRIES 20
> +
> +STATIC EFI_PHYSICAL_ADDRESS mTrngBaseAddress;
> +
> +/**
> + Returns information about the random number generation implementation.
> +
> + @param[in] This A pointer to the EFI_RNG_PROTOCOL
> + instance.
> + @param[in,out] RNGAlgorithmListSize On input, the size in bytes of
> + RNGAlgorithmList.
> + On output with a return code of
> + EFI_SUCCESS, the size in bytes of the
> + data returned in RNGAlgorithmList. On
> + output with a return code of
> + EFI_BUFFER_TOO_SMALL, the size of
> + RNGAlgorithmList required to obtain the
> + list.
> + @param[out] RNGAlgorithmList A caller-allocated memory buffer filled
> + by the driver with one EFI_RNG_ALGORITHM
> + element for each supported RNG algorithm.
> + The list must not change across multiple
> + calls to the same driver. The first
> + algorithm in the list is the default
> + algorithm for the driver.
> +
> + @retval EFI_SUCCESS The RNG algorithm list was returned
> + successfully.
> + @retval EFI_UNSUPPORTED The services is not supported by this
> + driver.
> + @retval EFI_DEVICE_ERROR The list of algorithms could not be
> + retrieved due to a hardware or firmware
> + error.
> + @retval EFI_INVALID_PARAMETER One or more of the parameters are
> + incorrect.
> + @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small
> + to hold the result.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +Armada70x0RngGetInfo (
> + IN EFI_RNG_PROTOCOL *This,
> + IN OUT UINTN *RNGAlgorithmListSize,
> + OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
> + )
> +{
> + if (This == NULL || RNGAlgorithmListSize == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if (*RNGAlgorithmListSize < sizeof (EFI_RNG_ALGORITHM)) {
> + *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
> + return EFI_BUFFER_TOO_SMALL;
> + }
> +
> + if (RNGAlgorithmList == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
> + CopyGuid (RNGAlgorithmList, &gEfiRngAlgorithmRaw);
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +GetTrngData (
> + IN UINTN Length,
> + OUT UINT8 *Bits
> + )
> +{
> + UINTN Tries;
> + UINT32 Buf[TRNG_OUTPUT_SIZE / sizeof (UINT32)];
> + UINTN Index;
> +
> + for (Tries = 0; Tries < TRNG_MAX_RETRIES; Tries++) {
> + if (MmioRead32 (TRNG_STATUS_REG) & TRNG_STATUS_READY) {
> + for (Index = 0; Index < ARRAY_SIZE (Buf); Index++) {
> + Buf[Index] = MmioRead32 (TRNG_OUTPUT_REG + Index * sizeof (UINT32));
> + }
> + CopyMem (Bits, Buf, Length);
> + MmioWrite32 (TRNG_INTACK_REG, TRNG_INTACK_READY);
> +
> + return EFI_SUCCESS;
> + }
> + // Wait for more TRNG data to arrive
> + gBS->Stall (10);
> + }
> + return EFI_DEVICE_ERROR;
> +}
> +
> +/**
> + Produces and returns an RNG value using either the default or specified RNG
> + algorithm.
> +
> + @param[in] This A pointer to the EFI_RNG_PROTOCOL
> + instance.
> + @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that
> + identifies the RNG algorithm to use. May
> + be NULL in which case the function will
> + use its default RNG algorithm.
> + @param[in] RNGValueLength The length in bytes of the memory buffer
> + pointed to by RNGValue. The driver shall
> + return exactly this numbers of bytes.
> + @param[out] RNGValue A caller-allocated memory buffer filled
> + by the driver with the resulting RNG
> + value.
> +
> + @retval EFI_SUCCESS The RNG value was returned successfully.
> + @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm
> + is not supported by this driver.
> + @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due
> + to a hardware or firmware error.
> + @retval EFI_NOT_READY There is not enough random data available
> + to satisfy the length requested by
> + RNGValueLength.
> + @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is
> + zero.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +Armada70x0RngGetRNG (
> + IN EFI_RNG_PROTOCOL *This,
> + IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL
> + IN UINTN RNGValueLength,
> + OUT UINT8 *RNGValue
> + )
> +{
> + UINTN Length;
> + EFI_STATUS Status;
> +
> + if (This == NULL || RNGValueLength == 0 || RNGValue == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // We only support the raw algorithm, so reject requests for anything else
> + //
> + if (RNGAlgorithm != NULL &&
> + !CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw)) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + do {
> + Length = MIN (RNGValueLength, TRNG_OUTPUT_SIZE);
> + Status = GetTrngData (Length, RNGValue);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + RNGValue += Length;
> + RNGValueLength -= Length;
> + } while (RNGValueLength > 0);
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC EFI_RNG_PROTOCOL mArmada70x0RngProtocol = {
> + Armada70x0RngGetInfo,
> + Armada70x0RngGetRNG
> +};
> +
> +//
> +// Entry point of this driver.
> +//
> +EFI_STATUS
> +EFIAPI
> +Armada70x0RngDxeEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + mTrngBaseAddress = PcdGet64 (PcdEip76TrngBaseAddress);
> +
> + //
> + // Disable the TRNG before updating its configuration
> + //
> + MmioAnd32 (TRNG_CONTROL_REG, ~TRNG_CONTROL_REG_ENABLE);
> +
> + //
> + // Configure the internal conditioning parameters of the TRNG
> + //
> + MmioWrite32 (TRNG_CONFIG_REG, TRNG_CONFIG_MIN_REFILL_CYCLES |
> + TRNG_CONFIG_MAX_REFILL_CYCLES);
> +
> + //
> + // Configure the FROs
> + //
> + MmioWrite32 (TRNG_FRODETUNE_REG, TRNG_FRODETUNE_MASK);
> + MmioWrite32 (TRNG_FROENABLE_REG, TRNG_FROENABLE_MASK);
> +
> + //
> + // Enable the TRNG
> + //
> + MmioOr32 (TRNG_CONTROL_REG, TRNG_CONTROL_REG_ENABLE);
> +
> + return SystemTable->BootServices->InstallMultipleProtocolInterfaces (
> + &ImageHandle,
> + &gEfiRngProtocolGuid,
> + &mArmada70x0RngProtocol,
> + NULL
> + );
> +}
> diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf
> new file mode 100644
> index 0000000..189ffc5
> --- /dev/null
> +++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf
> @@ -0,0 +1,47 @@
> +## @file
> +# This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TRNG
> +#
> +# Copyright (C) 2017, Linaro Ltd. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> +# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010019
> + BASE_NAME = Armada70x0RngDxe
> + FILE_GUID = dd87096a-cae5-4328-bec1-2ddb755f2e08
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = Armada70x0RngDxeEntryPoint
> +
> +[Sources]
> + Armada70x0RngDxe.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/Marvell/Marvell.dec
> +
> +[LibraryClasses]
> + BaseMemoryLib
> + IoLib
> + PcdLib
> + UefiDriverEntryPoint
> +
> +[Pcd]
> + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress
> +
> +[Protocols]
> + gEfiRngProtocolGuid ## PRODUCES
> +
> +[Guids]
> + gEfiRngAlgorithmRaw
> +
> +[Depex]
> + TRUE
> diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
> index e7d7c2c..78f5e53 100644
> --- a/Platform/Marvell/Marvell.dec
> +++ b/Platform/Marvell/Marvell.dec
> @@ -195,6 +195,9 @@
> #RTC
> gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052
>
> +#TRNG
> + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053
> +
> [Protocols]
> gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}
> gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }}
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [platforms: PATCH v2 2/8] Marvell/Armada: Increase preallocated memory region size
2017-10-25 6:45 [platforms: PATCH v2 0/8] Armada 7k/8k - memory improvements Marcin Wojtas
2017-10-25 6:45 ` [platforms: PATCH v2 1/8] Marvell/Armada: Implement EFI_RNG_PROTOCOL driver for EIP76 TRNG Marcin Wojtas
@ 2017-10-25 6:45 ` Marcin Wojtas
2017-10-25 6:45 ` [platforms: PATCH v2 3/8] Marvell/Armada: Remove custom reset library residues Marcin Wojtas
` (5 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2017-10-25 6:45 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, ard.biesheuvel, nadavh, neta, kostap, jinghua, mw,
jsd
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
In order to prevent fragmentation of the UEFI memory map, increase the
sizes of the preallocated regions. Note that this does not increase the
memory footprint of UEFI, it just modifies it allocation policy to keep
similar region types together.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Marvell/Armada/Armada.dsc.inc | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index ec24d76..56d8941 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -341,10 +341,10 @@
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|2000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|35000
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [platforms: PATCH v2 3/8] Marvell/Armada: Remove custom reset library residues
2017-10-25 6:45 [platforms: PATCH v2 0/8] Armada 7k/8k - memory improvements Marcin Wojtas
2017-10-25 6:45 ` [platforms: PATCH v2 1/8] Marvell/Armada: Implement EFI_RNG_PROTOCOL driver for EIP76 TRNG Marcin Wojtas
2017-10-25 6:45 ` [platforms: PATCH v2 2/8] Marvell/Armada: Increase preallocated memory region size Marcin Wojtas
@ 2017-10-25 6:45 ` Marcin Wojtas
2017-10-25 6:45 ` [platforms: PATCH v2 4/8] Marvell/Armada: Add support from DRAM remapping Marcin Wojtas
` (4 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2017-10-25 6:45 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, ard.biesheuvel, nadavh, neta, kostap, jinghua, mw,
jsd
When switching to generic PSCI reset library, obsolete parts
of previous custom reset library (PCDs, documentation) remained.
Remove them.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Marvell/Armada/Armada70x0.dsc | 4 ----
Platform/Marvell/Marvell.dec | 4 ----
Silicon/Marvell/Documentation/PortingGuide.txt | 9 ---------
3 files changed, 17 deletions(-)
diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc
index 430803c..946c93e 100644
--- a/Platform/Marvell/Armada/Armada70x0.dsc
+++ b/Platform/Marvell/Armada/Armada70x0.dsc
@@ -138,9 +138,5 @@
gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 }
gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
- #ResetLib
- gMarvellTokenSpaceGuid.PcdResetRegAddress|0xf06f0084
- gMarvellTokenSpaceGuid.PcdResetRegMask|0x1
-
#RTC
gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x1 }
diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
index 78f5e53..434d6cb 100644
--- a/Platform/Marvell/Marvell.dec
+++ b/Platform/Marvell/Marvell.dec
@@ -188,10 +188,6 @@
gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034
gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035
-#ResetLib
- gMarvellTokenSpaceGuid.PcdResetRegAddress|0|UINT64|0x40000050
- gMarvellTokenSpaceGuid.PcdResetRegMask|0|UINT32|0x4000051
-
#RTC
gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052
diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marvell/Documentation/PortingGuide.txt
index 66ec918..cbe3bed 100644
--- a/Silicon/Marvell/Documentation/PortingGuide.txt
+++ b/Silicon/Marvell/Documentation/PortingGuide.txt
@@ -383,15 +383,6 @@ Set pin 6 and 7 to 0xa function:
gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
-MarvellResetSystemLib configuration
-===================================
-This simple library allows to mask given bits in given reg at UEFI 'reset'
-command call. These variables are configurable through PCDs:
-
- - gMarvellTokenSpaceGuid.PcdResetRegAddress
- - gMarvellTokenSpaceGuid.PcdResetRegMask
-
-
Ramdisk configuration
=====================
There is one PCD available for Ramdisk configuration
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [platforms: PATCH v2 4/8] Marvell/Armada: Add support from DRAM remapping
2017-10-25 6:45 [platforms: PATCH v2 0/8] Armada 7k/8k - memory improvements Marcin Wojtas
` (2 preceding siblings ...)
2017-10-25 6:45 ` [platforms: PATCH v2 3/8] Marvell/Armada: Remove custom reset library residues Marcin Wojtas
@ 2017-10-25 6:45 ` Marcin Wojtas
2017-10-25 10:53 ` Leif Lindholm
2017-10-25 6:45 ` [platforms: PATCH v2 5/8] Marvell/Armada: Add MemoryInitPeiLib that reserves secure region Marcin Wojtas
` (3 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Marcin Wojtas @ 2017-10-25 6:45 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, ard.biesheuvel, nadavh, neta, kostap, jinghua, mw,
jsd
The Armada 70x0/80x0 DRAM controller allows a single window of DRAM
to be remapped to another location in the physical address space. This
allows us to free up some memory in the 32-bit addressable region for
peripheral MMIO and PCI MMIO32 and CONFIG spaces.
This patch adjusts memory blocks to the configuration done in ARM-TF.
The remap parameters are otained directly from the registers. Moreover,
the configuration space base address is now configurable via PCD, so
that to satisfy a case, when remap is not enabled in the early firmware
and ensure, that PcdSystemMemorySize is not overlapping it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 2 +
Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 90 +++++++++++++++-----
Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h | 48 +++++++++++
Platform/Marvell/Marvell.dec | 3 +
4 files changed, 124 insertions(+), 19 deletions(-)
diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
index 2e198c3..2236d9f 100644
--- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
+++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
@@ -67,5 +67,7 @@
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress
+
[Ppis]
gArmMpCoreInfoPpiGuid
diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
index 74c9956..978e4d3 100644
--- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
+++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
@@ -35,8 +35,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include <Base.h>
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
+#include "Armada70x0LibMem.h"
+
// The total number of descriptors, including the final "end-of-table" descriptor.
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16
@@ -44,6 +48,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS];
+
/**
Return the Virtual Memory Map of your platform
@@ -59,35 +65,81 @@ ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
UINTN Index = 0;
+ UINT64 MemSize;
+ UINT64 MemLowSize;
+ UINT64 MemHighStart;
+ UINT64 MemHighSize;
+ UINT64 ConfigSpaceBaseAddr;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
ASSERT (VirtualMemoryMap != NULL);
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
- if (VirtualMemoryTable == NULL) {
- return;
+ ConfigSpaceBaseAddr = FixedPcdGet64 (PcdConfigSpaceBaseAddress);
+
+ MemSize = FixedPcdGet64 (PcdSystemMemorySize);
+
+ if (DRAM_REMAP_ENABLED) {
+ MemLowSize = MIN (DRAM_REMAP_TARGET, MemSize);
+ MemHighStart = (UINT64)DRAM_REMAP_TARGET + DRAM_REMAP_SIZE;
+ MemHighSize = MemSize - MemLowSize;
+ } else {
+ MemLowSize = MIN (ConfigSpaceBaseAddr, MemSize);
}
- // DDR
- VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
- VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
- VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
- VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
+ ResourceAttributes = (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED
+ );
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ FixedPcdGet64 (PcdSystemMemoryBase),
+ MemLowSize
+ );
- // Configuration space 0xF000_0000 - 0xFFFF_FFFF
- VirtualMemoryTable[++Index].PhysicalBase = 0xF0000000;
- VirtualMemoryTable[Index].VirtualBase = 0xF0000000;
- VirtualMemoryTable[Index].Length = 0x10000000;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ // DDR
+ mVirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdSystemMemoryBase);
+ mVirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSystemMemoryBase);
+ mVirtualMemoryTable[Index].Length = MemLowSize;
+ mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
+
+ // Configuration space
+ mVirtualMemoryTable[++Index].PhysicalBase = ConfigSpaceBaseAddr;
+ mVirtualMemoryTable[Index].VirtualBase = ConfigSpaceBaseAddr;
+ mVirtualMemoryTable[Index].Length = SIZE_4GB - ConfigSpaceBaseAddr;
+ mVirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ if (MemSize > MemLowSize) {
+ //
+ // If we have more than MemLowSize worth of DRAM, the remainder will be
+ // mapped at the top of the remapped window.
+ //
+ mVirtualMemoryTable[++Index].PhysicalBase = MemHighStart;
+ mVirtualMemoryTable[Index].VirtualBase = MemHighStart;
+ mVirtualMemoryTable[Index].Length = MemHighSize;
+ mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ MemHighStart,
+ MemHighSize
+ );
+ }
// End of Table
- VirtualMemoryTable[++Index].PhysicalBase = 0;
- VirtualMemoryTable[Index].VirtualBase = 0;
- VirtualMemoryTable[Index].Length = 0;
- VirtualMemoryTable[Index].Attributes = 0;
+ mVirtualMemoryTable[++Index].PhysicalBase = 0;
+ mVirtualMemoryTable[Index].VirtualBase = 0;
+ mVirtualMemoryTable[Index].Length = 0;
+ mVirtualMemoryTable[Index].Attributes = 0;
ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
- *VirtualMemoryMap = VirtualMemoryTable;
+ *VirtualMemoryMap = mVirtualMemoryTable;
}
diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h
new file mode 100644
index 0000000..8101cf3
--- /dev/null
+++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h
@@ -0,0 +1,48 @@
+/*******************************************************************************
+Copyright (C) 2017 Marvell International Ltd.
+
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+* Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#define CCU_MC_RCR_REG 0xf0001700
+#define REMAP_EN_MASK 0x1
+#define REMAP_SIZE_OFFS 20
+#define REMAP_SIZE_MASK (0xfff << REMAP_SIZE_OFFS)
+#define CCU_MC_RTBR_REG 0xf0001708
+#define TARGET_BASE_OFFS 10
+#define TARGET_BASE_MASK (0xfffff << TARGET_BASE_OFFS)
+
+#define DRAM_REMAP_ENABLED \
+ (MmioRead32 (CCU_MC_RCR_REG) & REMAP_EN_MASK)
+#define DRAM_REMAP_SIZE \
+ (MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB
+#define DRAM_REMAP_TARGET \
+ (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS)
diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
index 434d6cb..36a9d59 100644
--- a/Platform/Marvell/Marvell.dec
+++ b/Platform/Marvell/Marvell.dec
@@ -194,6 +194,9 @@
#TRNG
gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053
+#Configuration space
+ gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT64|0x50000054
+
[Protocols]
gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}
gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }}
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [platforms: PATCH v2 4/8] Marvell/Armada: Add support from DRAM remapping
2017-10-25 6:45 ` [platforms: PATCH v2 4/8] Marvell/Armada: Add support from DRAM remapping Marcin Wojtas
@ 2017-10-25 10:53 ` Leif Lindholm
0 siblings, 0 replies; 12+ messages in thread
From: Leif Lindholm @ 2017-10-25 10:53 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel, ard.biesheuvel, nadavh, neta, kostap, jinghua, jsd
Subject line still wrong. from -> for
On Wed, Oct 25, 2017 at 08:45:26AM +0200, Marcin Wojtas wrote:
> The Armada 70x0/80x0 DRAM controller allows a single window of DRAM
> to be remapped to another location in the physical address space.
Since DRAM starts at address 0, and normally exceeds 4GB on these
systems, this ...
content below is fine.
/
Leif
> This
> allows us to free up some memory in the 32-bit addressable region for
> peripheral MMIO and PCI MMIO32 and CONFIG spaces.
>
> This patch adjusts memory blocks to the configuration done in ARM-TF.
> The remap parameters are otained directly from the registers. Moreover,
> the configuration space base address is now configurable via PCD, so
> that to satisfy a case, when remap is not enabled in the early firmware
> and ensure, that PcdSystemMemorySize is not overlapping it.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
> Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 2 +
> Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 90 +++++++++++++++-----
> Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h | 48 +++++++++++
> Platform/Marvell/Marvell.dec | 3 +
> 4 files changed, 124 insertions(+), 19 deletions(-)
>
> diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
> index 2e198c3..2236d9f 100644
> --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
> +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
> @@ -67,5 +67,7 @@
> gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> gArmTokenSpaceGuid.PcdArmPrimaryCore
>
> + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress
> +
> [Ppis]
> gArmMpCoreInfoPpiGuid
> diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
> index 74c9956..978e4d3 100644
> --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
> +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
> @@ -35,8 +35,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> #include <Base.h>
> #include <Library/ArmPlatformLib.h>
> #include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/IoLib.h>
> #include <Library/MemoryAllocationLib.h>
>
> +#include "Armada70x0LibMem.h"
> +
> // The total number of descriptors, including the final "end-of-table" descriptor.
> #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16
>
> @@ -44,6 +48,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
> #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
>
> +STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS];
> +
> /**
> Return the Virtual Memory Map of your platform
>
> @@ -59,35 +65,81 @@ ArmPlatformGetVirtualMemoryMap (
> IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
> )
> {
> - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> UINTN Index = 0;
> + UINT64 MemSize;
> + UINT64 MemLowSize;
> + UINT64 MemHighStart;
> + UINT64 MemHighSize;
> + UINT64 ConfigSpaceBaseAddr;
> + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
>
> ASSERT (VirtualMemoryMap != NULL);
>
> - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> - if (VirtualMemoryTable == NULL) {
> - return;
> + ConfigSpaceBaseAddr = FixedPcdGet64 (PcdConfigSpaceBaseAddress);
> +
> + MemSize = FixedPcdGet64 (PcdSystemMemorySize);
> +
> + if (DRAM_REMAP_ENABLED) {
> + MemLowSize = MIN (DRAM_REMAP_TARGET, MemSize);
> + MemHighStart = (UINT64)DRAM_REMAP_TARGET + DRAM_REMAP_SIZE;
> + MemHighSize = MemSize - MemLowSize;
> + } else {
> + MemLowSize = MIN (ConfigSpaceBaseAddr, MemSize);
> }
>
> - // DDR
> - VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
> - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
> - VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
> - VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
> + ResourceAttributes = (
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_TESTED
> + );
> +
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + FixedPcdGet64 (PcdSystemMemoryBase),
> + MemLowSize
> + );
>
> - // Configuration space 0xF000_0000 - 0xFFFF_FFFF
> - VirtualMemoryTable[++Index].PhysicalBase = 0xF0000000;
> - VirtualMemoryTable[Index].VirtualBase = 0xF0000000;
> - VirtualMemoryTable[Index].Length = 0x10000000;
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> + // DDR
> + mVirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdSystemMemoryBase);
> + mVirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSystemMemoryBase);
> + mVirtualMemoryTable[Index].Length = MemLowSize;
> + mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
> +
> + // Configuration space
> + mVirtualMemoryTable[++Index].PhysicalBase = ConfigSpaceBaseAddr;
> + mVirtualMemoryTable[Index].VirtualBase = ConfigSpaceBaseAddr;
> + mVirtualMemoryTable[Index].Length = SIZE_4GB - ConfigSpaceBaseAddr;
> + mVirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + if (MemSize > MemLowSize) {
> + //
> + // If we have more than MemLowSize worth of DRAM, the remainder will be
> + // mapped at the top of the remapped window.
> + //
> + mVirtualMemoryTable[++Index].PhysicalBase = MemHighStart;
> + mVirtualMemoryTable[Index].VirtualBase = MemHighStart;
> + mVirtualMemoryTable[Index].Length = MemHighSize;
> + mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
> +
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + MemHighStart,
> + MemHighSize
> + );
> + }
>
> // End of Table
> - VirtualMemoryTable[++Index].PhysicalBase = 0;
> - VirtualMemoryTable[Index].VirtualBase = 0;
> - VirtualMemoryTable[Index].Length = 0;
> - VirtualMemoryTable[Index].Attributes = 0;
> + mVirtualMemoryTable[++Index].PhysicalBase = 0;
> + mVirtualMemoryTable[Index].VirtualBase = 0;
> + mVirtualMemoryTable[Index].Length = 0;
> + mVirtualMemoryTable[Index].Attributes = 0;
>
> ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
>
> - *VirtualMemoryMap = VirtualMemoryTable;
> + *VirtualMemoryMap = mVirtualMemoryTable;
> }
> diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h
> new file mode 100644
> index 0000000..8101cf3
> --- /dev/null
> +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h
> @@ -0,0 +1,48 @@
> +/*******************************************************************************
> +Copyright (C) 2017 Marvell International Ltd.
> +
> +Marvell BSD License Option
> +
> +If you received this File from Marvell, you may opt to use, redistribute and/or
> +modify this File under the following licensing terms.
> +Redistribution and use in source and binary forms, with or without modification,
> +are permitted provided that the following conditions are met:
> +
> +* Redistributions of source code must retain the above copyright notice,
> + this list of conditions and the following disclaimer.
> +
> +* Redistributions in binary form must reproduce the above copyright
> + notice, this list of conditions and the following disclaimer in the
> + documentation and/or other materials provided with the distribution.
> +
> +* Neither the name of Marvell nor the names of its contributors may be
> + used to endorse or promote products derived from this software without
> + specific prior written permission.
> +
> +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
> +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
> +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
> +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
> +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
> +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
> +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> +
> +*******************************************************************************/
> +
> +#define CCU_MC_RCR_REG 0xf0001700
> +#define REMAP_EN_MASK 0x1
> +#define REMAP_SIZE_OFFS 20
> +#define REMAP_SIZE_MASK (0xfff << REMAP_SIZE_OFFS)
> +#define CCU_MC_RTBR_REG 0xf0001708
> +#define TARGET_BASE_OFFS 10
> +#define TARGET_BASE_MASK (0xfffff << TARGET_BASE_OFFS)
> +
> +#define DRAM_REMAP_ENABLED \
> + (MmioRead32 (CCU_MC_RCR_REG) & REMAP_EN_MASK)
> +#define DRAM_REMAP_SIZE \
> + (MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB
> +#define DRAM_REMAP_TARGET \
> + (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS)
> diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
> index 434d6cb..36a9d59 100644
> --- a/Platform/Marvell/Marvell.dec
> +++ b/Platform/Marvell/Marvell.dec
> @@ -194,6 +194,9 @@
> #TRNG
> gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053
>
> +#Configuration space
> + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT64|0x50000054
> +
> [Protocols]
> gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}
> gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }}
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [platforms: PATCH v2 5/8] Marvell/Armada: Add MemoryInitPeiLib that reserves secure region
2017-10-25 6:45 [platforms: PATCH v2 0/8] Armada 7k/8k - memory improvements Marcin Wojtas
` (3 preceding siblings ...)
2017-10-25 6:45 ` [platforms: PATCH v2 4/8] Marvell/Armada: Add support from DRAM remapping Marcin Wojtas
@ 2017-10-25 6:45 ` Marcin Wojtas
2017-10-25 6:45 ` [platforms: PATCH v2 6/8] Marvell/Armada: Enable dynamic DRAM size detection Marcin Wojtas
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2017-10-25 6:45 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, ard.biesheuvel, nadavh, neta, kostap, jinghua, mw,
jsd
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
The default MemoryInitPeiLib implementation insists on reserving the
region occupied by our own FV, while this is not necessary at all (the
compressed payload is uncompressed elsewhere, so the moment we enter
DXE core, we don't care about the FV contents in memory)
So clone MemoryInitPeiLib and modify it to suit our needs.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Marvell/Armada/Armada.dsc.inc | 6 +-
Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c | 158 ++++++++++++++++++++
Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf | 46 ++++++
Platform/Marvell/Marvell.dec | 8 +
4 files changed, 217 insertions(+), 1 deletion(-)
diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index 56d8941..b0a8240 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -153,7 +153,7 @@
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
[LibraryClasses.common.SEC, LibraryClasses.common.PEIM]
- MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+ MemoryInitPeiLib|Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
[LibraryClasses.common.DXE_CORE]
@@ -364,6 +364,10 @@
gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
gArmTokenSpaceGuid.PcdArmScr|0x531
+ # Secure region reservation
+ gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000
+ gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0200000
+
# TRNG
gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000
diff --git a/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c
new file mode 100644
index 0000000..53119f4
--- /dev/null
+++ b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.c
@@ -0,0 +1,158 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2017, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiPei.h>
+
+#include <Library/ArmMmuLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+
+VOID
+BuildMemoryTypeInformationHob (
+ VOID
+ );
+
+STATIC
+VOID
+InitMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
+ )
+{
+
+ VOID *TranslationTableBase;
+ UINTN TranslationTableSize;
+ RETURN_STATUS Status;
+
+ Status = ArmConfigureMmu (MemoryTable,
+ &TranslationTableBase,
+ &TranslationTableSize);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n"));
+ }
+}
+
+/*++
+
+Routine Description:
+
+
+
+Arguments:
+
+ FileHandle - Handle of the file being invoked.
+ PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+ Status - EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+ UINT64 ResourceLength;
+ EFI_PEI_HOB_POINTERS NextHob;
+ EFI_PHYSICAL_ADDRESS SecureTop;
+ EFI_PHYSICAL_ADDRESS ResourceTop;
+
+ // Get Virtual Memory Map from the Platform Library
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
+ SecureTop = (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdSecureRegionBase) +
+ FixedPcdGet32 (PcdSecureRegionSize);
+
+ //
+ // Search for System Memory Hob that covers the secure firmware,
+ // and punch a hole in it
+ //
+ for (NextHob.Raw = GetHobList ();
+ NextHob.Raw != NULL;
+ NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,
+ NextHob.Raw)) {
+
+ if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
+ (FixedPcdGet64 (PcdSecureRegionBase) >= NextHob.ResourceDescriptor->PhysicalStart) &&
+ (SecureTop <= NextHob.ResourceDescriptor->PhysicalStart +
+ NextHob.ResourceDescriptor->ResourceLength))
+ {
+ ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
+ ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
+ ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
+
+ if (FixedPcdGet64 (PcdSecureRegionBase) == NextHob.ResourceDescriptor->PhysicalStart) {
+ //
+ // This region starts right at the start of the reserved region, so we
+ // can simply move its start pointer and reduce its length by the same
+ // value
+ //
+ NextHob.ResourceDescriptor->PhysicalStart += FixedPcdGet32 (PcdSecureRegionSize);
+ NextHob.ResourceDescriptor->ResourceLength -= FixedPcdGet32 (PcdSecureRegionSize);
+
+ } else if ((NextHob.ResourceDescriptor->PhysicalStart +
+ NextHob.ResourceDescriptor->ResourceLength) == SecureTop) {
+
+ //
+ // This region ends right at the end of the reserved region, so we
+ // can simply reduce its length by the size of the region.
+ //
+ NextHob.ResourceDescriptor->ResourceLength -= FixedPcdGet32 (PcdSecureRegionSize);
+
+ } else {
+ //
+ // This region covers the reserved region. So split it into two regions,
+ // each one touching the reserved region at either end, but not covering
+ // it.
+ //
+ NextHob.ResourceDescriptor->ResourceLength = FixedPcdGet64 (PcdSecureRegionBase) -
+ NextHob.ResourceDescriptor->PhysicalStart;
+
+ // Create the System Memory HOB for the remaining region (top of the FD)
+ BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ SecureTop,
+ ResourceTop - SecureTop);
+ }
+
+ //
+ // Reserve the memory space occupied by the secure firmware
+ //
+ BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED,
+ 0,
+ FixedPcdGet64 (PcdSecureRegionBase),
+ FixedPcdGet32 (PcdSecureRegionSize));
+
+ break;
+ }
+ NextHob.Raw = GET_NEXT_HOB (NextHob);
+ }
+
+ // Build Memory Allocation Hob
+ InitMmu (MemoryTable);
+
+ if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
+ // Optional feature that helps prevent EFI memory map fragmentation.
+ BuildMemoryTypeInformationHob ();
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf
new file mode 100644
index 0000000..ebaed01
--- /dev/null
+++ b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0MemoryInitPeiLib.inf
@@ -0,0 +1,46 @@
+#/** @file
+#
+# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = Armada70x0MemoryInitPeiLib
+ FILE_GUID = abc4e8a7-89a7-4aea-92bc-0e9421c4a473
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM
+
+[Sources]
+ Armada70x0MemoryInitPeiLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/Marvell/Marvell.dec
+
+[LibraryClasses]
+ ArmPlatformLib
+ DebugLib
+ HobLib
+ ArmMmuLib
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+
+[FixedPcd]
+ gMarvellTokenSpaceGuid.PcdSecureRegionBase
+ gMarvellTokenSpaceGuid.PcdSecureRegionSize
diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
index 36a9d59..cd800c8 100644
--- a/Platform/Marvell/Marvell.dec
+++ b/Platform/Marvell/Marvell.dec
@@ -197,6 +197,14 @@
#Configuration space
gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT64|0x50000054
+ #
+ # The secure firmware may occupy a DRAM region that is accessible by the
+ # normal world. These PCDs describe such a region, which will be converted
+ # to 'reserved' memory before DXE is entered.
+ #
+ gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x0|UINT64|0x50000000
+ gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0|UINT32|0x50000001
+
[Protocols]
gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}
gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }}
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [platforms: PATCH v2 6/8] Marvell/Armada: Enable dynamic DRAM size detection
2017-10-25 6:45 [platforms: PATCH v2 0/8] Armada 7k/8k - memory improvements Marcin Wojtas
` (4 preceding siblings ...)
2017-10-25 6:45 ` [platforms: PATCH v2 5/8] Marvell/Armada: Add MemoryInitPeiLib that reserves secure region Marcin Wojtas
@ 2017-10-25 6:45 ` Marcin Wojtas
2017-10-25 12:26 ` Leif Lindholm
2017-10-25 6:45 ` [platforms: PATCH v2 7/8] Marvell/Armada: Armada70x0Lib: Add support for 32-bit ARM Marcin Wojtas
2017-10-25 6:45 ` [platforms: PATCH v2 8/8] Marvell/Armada: Add 32-bit ARM support Marcin Wojtas
7 siblings, 1 reply; 12+ messages in thread
From: Marcin Wojtas @ 2017-10-25 6:45 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, ard.biesheuvel, nadavh, neta, kostap, jinghua, mw,
jsd
Instead of using hardcoded value in PcdSystemMemorySize PCD,
obtain DRAM size directly from SoC registers, which are filled
by firmware during early initialization stage.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 62 +++++++++++++++++++-
Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h | 25 ++++++++
2 files changed, 86 insertions(+), 1 deletion(-)
diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
index 978e4d3..bf0ebcf 100644
--- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
+++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
@@ -50,6 +50,60 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS];
+// Obtain DRAM size basing on register values filled by early firmware.
+STATIC
+UINT64
+GetDramSize (
+ IN OUT UINT64 *MemSize
+ )
+{
+ UINT64 BaseAddr;
+ UINT8 RegionCode;
+ UINT8 Cs;
+
+ *MemSize = 0;
+
+ for (Cs = 0; Cs < DRAM_MAX_CS_NUM; Cs++) {
+
+ /* Exit loop on first disabled DRAM CS */
+ if (!DRAM_CS_ENABLED (Cs)) {
+ break;
+ }
+
+ /*
+ * Sanity check for base address of next DRAM block.
+ * Only continuous space will be used.
+ */
+ BaseAddr = GET_DRAM_REGION_BASE (Cs);
+ if (BaseAddr != *MemSize) {
+ DEBUG ((DEBUG_ERROR,
+ "%a: DRAM blocks are not contiguous, limit size to 0x%llx\n",
+ __FUNCTION__,
+ *MemSize));
+ return EFI_SUCCESS;
+ }
+
+ /* Decode area length for current CS from register value */
+ RegionCode = GET_DRAM_REGION_SIZE_CODE (Cs);
+ if (DRAM_REGION_SIZE_CODE_INVALID (RegionCode)) {
+ DEBUG ((DEBUG_ERROR,
+ "%a: Invalid memory region code (0x%x) for CS#%d\n",
+ __FUNCTION__,
+ RegionCode,
+ Cs));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (RegionCode <= 0x4) {
+ *MemSize += GET_DRAM_REGION_SIZE_ODD (RegionCode);
+ } else {
+ *MemSize += GET_DRAM_REGION_SIZE_EVEN (RegionCode);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
/**
Return the Virtual Memory Map of your platform
@@ -72,12 +126,18 @@ ArmPlatformGetVirtualMemoryMap (
UINT64 MemHighSize;
UINT64 ConfigSpaceBaseAddr;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+ EFI_STATUS Status;
ASSERT (VirtualMemoryMap != NULL);
ConfigSpaceBaseAddr = FixedPcdGet64 (PcdConfigSpaceBaseAddress);
- MemSize = FixedPcdGet64 (PcdSystemMemorySize);
+ // Obtain total memory size from the hardware.
+ Status = GetDramSize (&MemSize);
+ if (EFI_ERROR (Status)) {
+ MemSize = FixedPcdGet64 (PcdSystemMemorySize);
+ DEBUG ((DEBUG_ERROR, "Limit total memory size to %d MB\n", MemSize / 1024 / 1024));
+ }
if (DRAM_REMAP_ENABLED) {
MemLowSize = MIN (DRAM_REMAP_TARGET, MemSize);
diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h
index 8101cf3..dd218d9 100644
--- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h
+++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h
@@ -46,3 +46,28 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
(MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB
#define DRAM_REMAP_TARGET \
(MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS)
+
+#define DRAM_CH0_MMAP_LOW_REG(cs) (0xf0020200 + (cs) * 0x8)
+#define DRAM_CS_VALID_ENABLED_MASK 0x1
+#define DRAM_AREA_LENGTH_OFFS 16
+#define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS)
+#define DRAM_START_ADDRESS_L_OFFS 23
+#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFFS)
+#define DRAM_CH0_MMAP_HIGH_REG(cs) (0xf0020204 + (cs) * 0x8)
+#define DRAM_START_ADDR_HTOL_OFFS 32
+
+#define DRAM_MAX_CS_NUM 8
+
+#define DRAM_CS_ENABLED(Cs) \
+ (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_CS_VALID_ENABLED_MASK)
+#define GET_DRAM_REGION_BASE(Cs) \
+ ((UINT64)MmioRead32 (DRAM_CH0_MMAP_HIGH_REG ((Cs))) << \
+ DRAM_START_ADDR_HTOL_OFFS) | \
+ (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_START_ADDRESS_L_MASK);
+#define GET_DRAM_REGION_SIZE_CODE(Cs) \
+ (MmioRead32 (DRAM_CH0_MMAP_LOW_REG ((Cs))) & \
+ DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS
+#define DRAM_REGION_SIZE_CODE_INVALID(C) \
+ (((C) > 0x4 && (C) < 0x7) || (C) > 0x1b)
+#define GET_DRAM_REGION_SIZE_ODD(C) ((UINT64)0x18000000 << (C))
+#define GET_DRAM_REGION_SIZE_EVEN(C) ((UINT64)1 << ((C) + 16))
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [platforms: PATCH v2 6/8] Marvell/Armada: Enable dynamic DRAM size detection
2017-10-25 6:45 ` [platforms: PATCH v2 6/8] Marvell/Armada: Enable dynamic DRAM size detection Marcin Wojtas
@ 2017-10-25 12:26 ` Leif Lindholm
0 siblings, 0 replies; 12+ messages in thread
From: Leif Lindholm @ 2017-10-25 12:26 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel, ard.biesheuvel, nadavh, neta, kostap, jinghua, jsd
On Wed, Oct 25, 2017 at 08:45:28AM +0200, Marcin Wojtas wrote:
> Instead of using hardcoded value in PcdSystemMemorySize PCD,
> obtain DRAM size directly from SoC registers, which are filled
> by firmware during early initialization stage.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 62 +++++++++++++++++++-
> Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h | 25 ++++++++
> 2 files changed, 86 insertions(+), 1 deletion(-)
>
> diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
> index 978e4d3..bf0ebcf 100644
> --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
> +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c
> @@ -50,6 +50,60 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>
> STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS];
>
> +// Obtain DRAM size basing on register values filled by early firmware.
> +STATIC
> +UINT64
> +GetDramSize (
> + IN OUT UINT64 *MemSize
> + )
> +{
> + UINT64 BaseAddr;
> + UINT8 RegionCode;
> + UINT8 Cs;
> +
> + *MemSize = 0;
> +
> + for (Cs = 0; Cs < DRAM_MAX_CS_NUM; Cs++) {
> +
> + /* Exit loop on first disabled DRAM CS */
> + if (!DRAM_CS_ENABLED (Cs)) {
> + break;
> + }
> +
> + /*
> + * Sanity check for base address of next DRAM block.
> + * Only continuous space will be used.
> + */
> + BaseAddr = GET_DRAM_REGION_BASE (Cs);
> + if (BaseAddr != *MemSize) {
> + DEBUG ((DEBUG_ERROR,
> + "%a: DRAM blocks are not contiguous, limit size to 0x%llx\n",
> + __FUNCTION__,
> + *MemSize));
> + return EFI_SUCCESS;
> + }
> +
> + /* Decode area length for current CS from register value */
> + RegionCode = GET_DRAM_REGION_SIZE_CODE (Cs);
> + if (DRAM_REGION_SIZE_CODE_INVALID (RegionCode)) {
> + DEBUG ((DEBUG_ERROR,
> + "%a: Invalid memory region code (0x%x) for CS#%d\n",
> + __FUNCTION__,
> + RegionCode,
> + Cs));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if (RegionCode <= 0x4) {
It would be even nicer this one could be abstracted away in another
macro (now everything else is this clean, it does sort of stand out).
> + *MemSize += GET_DRAM_REGION_SIZE_ODD (RegionCode);
> + } else {
> + *MemSize += GET_DRAM_REGION_SIZE_EVEN (RegionCode);
> + }
I guess we should also check for the reserved ones.
I'm also a fan of the "common case first" approach to if-statements.
So, could we squash these two together?:
if (DRAM_REGION_SIZE_EVEN (RegionCode)) {
*MemSize += GET_DRAM_REGION_SIZE_EVEN (RegionCode);
} else if (DRAM_REGION_SIZE_ODD (RegionCode)) {
*MemSize += GET_DRAM_REGION_SIZE_ODD (RegionCode);
} else {
DEBUG ((DEBUG_ERROR,
"%a: Invalid memory region code (0x%x) for CS#%d\n",
__FUNCTION__,
RegionCode,
Cs));
return EFI_INVALID_PARAMETER;
}
Where
#define DRAM_REGION_SIZE_ODD(x) ((x) <= 4)
#define DRAM_REGION_SIZE_EVEN(x) (((x) >= 7) && ((x) <= 26))
(I use decimal numbers, because so does the documentation.)
/
Leif
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> /**
> Return the Virtual Memory Map of your platform
>
> @@ -72,12 +126,18 @@ ArmPlatformGetVirtualMemoryMap (
> UINT64 MemHighSize;
> UINT64 ConfigSpaceBaseAddr;
> EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> + EFI_STATUS Status;
>
> ASSERT (VirtualMemoryMap != NULL);
>
> ConfigSpaceBaseAddr = FixedPcdGet64 (PcdConfigSpaceBaseAddress);
>
> - MemSize = FixedPcdGet64 (PcdSystemMemorySize);
> + // Obtain total memory size from the hardware.
> + Status = GetDramSize (&MemSize);
> + if (EFI_ERROR (Status)) {
> + MemSize = FixedPcdGet64 (PcdSystemMemorySize);
> + DEBUG ((DEBUG_ERROR, "Limit total memory size to %d MB\n", MemSize / 1024 / 1024));
> + }
>
> if (DRAM_REMAP_ENABLED) {
> MemLowSize = MIN (DRAM_REMAP_TARGET, MemSize);
> diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h
> index 8101cf3..dd218d9 100644
> --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h
> +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h
> @@ -46,3 +46,28 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> (MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB
> #define DRAM_REMAP_TARGET \
> (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS)
> +
> +#define DRAM_CH0_MMAP_LOW_REG(cs) (0xf0020200 + (cs) * 0x8)
> +#define DRAM_CS_VALID_ENABLED_MASK 0x1
> +#define DRAM_AREA_LENGTH_OFFS 16
> +#define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS)
> +#define DRAM_START_ADDRESS_L_OFFS 23
> +#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFFS)
> +#define DRAM_CH0_MMAP_HIGH_REG(cs) (0xf0020204 + (cs) * 0x8)
> +#define DRAM_START_ADDR_HTOL_OFFS 32
> +
> +#define DRAM_MAX_CS_NUM 8
> +
> +#define DRAM_CS_ENABLED(Cs) \
> + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_CS_VALID_ENABLED_MASK)
> +#define GET_DRAM_REGION_BASE(Cs) \
> + ((UINT64)MmioRead32 (DRAM_CH0_MMAP_HIGH_REG ((Cs))) << \
> + DRAM_START_ADDR_HTOL_OFFS) | \
> + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_START_ADDRESS_L_MASK);
> +#define GET_DRAM_REGION_SIZE_CODE(Cs) \
> + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG ((Cs))) & \
> + DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS
> +#define DRAM_REGION_SIZE_CODE_INVALID(C) \
> + (((C) > 0x4 && (C) < 0x7) || (C) > 0x1b)
> +#define GET_DRAM_REGION_SIZE_ODD(C) ((UINT64)0x18000000 << (C))
> +#define GET_DRAM_REGION_SIZE_EVEN(C) ((UINT64)1 << ((C) + 16))
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [platforms: PATCH v2 7/8] Marvell/Armada: Armada70x0Lib: Add support for 32-bit ARM
2017-10-25 6:45 [platforms: PATCH v2 0/8] Armada 7k/8k - memory improvements Marcin Wojtas
` (5 preceding siblings ...)
2017-10-25 6:45 ` [platforms: PATCH v2 6/8] Marvell/Armada: Enable dynamic DRAM size detection Marcin Wojtas
@ 2017-10-25 6:45 ` Marcin Wojtas
2017-10-25 6:45 ` [platforms: PATCH v2 8/8] Marvell/Armada: Add 32-bit ARM support Marcin Wojtas
7 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2017-10-25 6:45 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, ard.biesheuvel, nadavh, neta, kostap, jinghua, mw,
jsd
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Add an ARM implementation of ArmPlatformHelper.S.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S | 77 ++++++++++++++++++++
Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 3 +
2 files changed, 80 insertions(+)
diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S
new file mode 100644
index 0000000..21459e5
--- /dev/null
+++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S
@@ -0,0 +1,77 @@
+//Based on ArmPlatformPkg/Library/ArmPlatformLibNull/AArch64/ArmPlatformHelper.S
+//
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+// Copyright (c) 2016, Marvell. All rights reserved.
+// Copyright (c) 2017, Linaro Limited. All rights reserved.
+//
+// This program and the accompanying materials are licensed and made available
+// under the terms and conditions of the BSD License which accompanies this
+// distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED
+//
+
+#include <AsmMacroIoLib.h>
+#include <Library/ArmLib.h>
+
+#define CCU_MC_BASE 0xF0001700
+#define CCU_MC_RCR_OFFSET 0x0
+#define CCU_MC_RCR_REMAP_EN BIT0
+#define CCU_MC_RCR_REMAP_SIZE(Size) (((Size) - 1) ^ (SIZE_1MB - 1))
+
+#define CCU_MC_RSBR_OFFSET 0x4
+#define CCU_MC_RSBR_SOURCE_BASE(Base) (((Base) >> 20) << 10)
+#define CCU_MC_RTBR_OFFSET 0x8
+#define CCU_MC_RTBR_TARGET_BASE(Base) (((Base) >> 20) << 10)
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ .if FixedPcdGet64 (PcdSystemMemoryBase) != 0
+ .err PcdSystemMemoryBase should be 0x0 on this platform!
+ .endif
+
+ .if FixedPcdGet64 (PcdSystemMemorySize) > FixedPcdGet32 (PcdDramRemapTarget)
+ //
+ // Use the low range for UEFI itself. The remaining memory will be mapped
+ // and added to the GCD map later.
+ //
+ ADRL (r0, mSystemMemoryEnd)
+ MOV32 (r2, FixedPcdGet32 (PcdDramRemapTarget) - 1)
+ mov r3, #0
+ strd r2, r3, [r0]
+ .endif
+
+ bx lr
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+ and r1, r0, #ARM_CORE_MASK
+ and r0, r0, #ARM_CLUSTER_MASK
+ add r0, r1, r0, LSR #7
+ bx lr
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (r0, FixedPcdGet32(PcdArmPrimaryCore))
+ bx lr
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ MOV32 (r1, FixedPcdGet32(PcdArmPrimaryCoreMask))
+ and r0, r0, r1
+ MOV32 (r1, FixedPcdGet32(PcdArmPrimaryCore))
+ cmp r0, r1
+ moveq r0, #1
+ movne r0, #0
+ bx lr
diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
index 2236d9f..71abdd4 100644
--- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
+++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf
@@ -60,6 +60,9 @@
[Sources.AArch64]
AArch64/ArmPlatformHelper.S
+[Sources.ARM]
+ ARM/ArmPlatformHelper.S
+
[FixedPcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [platforms: PATCH v2 8/8] Marvell/Armada: Add 32-bit ARM support
2017-10-25 6:45 [platforms: PATCH v2 0/8] Armada 7k/8k - memory improvements Marcin Wojtas
` (6 preceding siblings ...)
2017-10-25 6:45 ` [platforms: PATCH v2 7/8] Marvell/Armada: Armada70x0Lib: Add support for 32-bit ARM Marcin Wojtas
@ 2017-10-25 6:45 ` Marcin Wojtas
7 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2017-10-25 6:45 UTC (permalink / raw)
To: edk2-devel
Cc: leif.lindholm, ard.biesheuvel, nadavh, neta, kostap, jinghua, mw,
jsd
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Update the included components and library classes to make this platform
build for 32-bit ARM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Marvell/Armada/Armada.dsc.inc | 3 +--
Platform/Marvell/Armada/Armada70x0.dsc | 4 ++--
Platform/Marvell/Armada/Armada70x0.fdf | 2 +-
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index b0a8240..b9fc384 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -132,7 +132,6 @@
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
-[LibraryClasses.AARCH64]
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
@@ -362,7 +361,7 @@
# ARM Pcds
gArmTokenSpaceGuid.PcdSystemMemoryBase|0
gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
- gArmTokenSpaceGuid.PcdArmScr|0x531
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36
# Secure region reservation
gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000
diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc
index 946c93e..0396e8e 100644
--- a/Platform/Marvell/Armada/Armada70x0.dsc
+++ b/Platform/Marvell/Armada/Armada70x0.dsc
@@ -39,8 +39,8 @@
PLATFORM_GUID = f837e231-cfc7-4f56-9a0f-5b218d746ae3
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
- OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
- SUPPORTED_ARCHITECTURES = AARCH64
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
FLASH_DEFINITION = Platform/Marvell/Armada/Armada70x0.fdf
diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Armada/Armada70x0.fdf
index a94a9ff..ec2c368 100644
--- a/Platform/Marvell/Armada/Armada70x0.fdf
+++ b/Platform/Marvell/Armada/Armada70x0.fdf
@@ -237,7 +237,7 @@ READ_LOCK_STATUS = TRUE
#
############################################################################
-[Rule.AARCH64.SEC]
+[Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
}
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread