From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F233F2034C084 for ; Tue, 24 Oct 2017 23:43:07 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id 75so26580862lfx.1 for ; Tue, 24 Oct 2017 23:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LCLvu6jJfaLlMbFHtMxK9V9F+VtE+0HlgrjYt5tfUbI=; b=zNfyaBiF+KPL5CLpW2A3IHPF2NXW0IN5b2O6DPvJvdupUWVR0cvlTtXpG+mk1OLEeJ x0MW01Y7Ww0cqvYIqy9vO8sBJQX7vdk/Vh0Om98+1O6nqsDStj0ow8Al6yx+p0dxu1Ey 7t6WFNKRiXBPJ2/V8AMB7hPY8farNsH8mTOXsAYZFg/zpXGLmAbnnQPZdvrAc+DOakYV tWS22bzW5/I/I7O4uCIwaho5PUIlP5B8B1VbvA/MMqih0uxLwb7Me7/09N3EzE9HUzVC FQNKj3e2T7VlftCnETc+3ygewnTLYp+1etX6g1fErPzUyD3qFzivgk4SdIOuoYcGMtZk 2lVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LCLvu6jJfaLlMbFHtMxK9V9F+VtE+0HlgrjYt5tfUbI=; b=c5h5JbeihWGcD3nUS0YR6iyJ4bMZ6a/yFbjMt8APoM/SsQFEo8q9FA/OG58/5rruFb E+v8tSS3TVnEoQrGDgFmrCOsNO5Ghv8tYqbkPEBlQ+1AEHDKIoXQteNuQLsPQGK+Orde JzIn+YnZVKzTHO1AsQ81mWQG7tsXob7jKebXsYdVwuKQv2bXxYdt0R6ArwvoVqi3nOUe FbzQbdU88AIVXd/+WqKPeF9UKWKu3VhjGbwffLf0uVWuO0EGe0fzgqKGFQRnBOVGPLuO ZtwmUyc6SlrV2DwiSVXRqlMKKgkpZfkGr+WneOFs4CHX8ejXHP2J6jurIqYpvKgF/z3y nX8g== X-Gm-Message-State: AMCzsaWMvSd0Ma665Lu7AcRB7DFzbTUpz2rn6bfkOGofAmrlGAkDwatA TblRw115MBWrhV1/dH8gkGGNCH1fKoU= X-Google-Smtp-Source: ABhQp+Q9eC3U64C8DDGytEhWh14b0pz5aN8E6Pd1P+hFLx/lCHBvtlKGo/euC9yCwYTpwNan79HDDQ== X-Received: by 10.46.43.145 with SMTP id r17mr7710972ljr.56.1508914010873; Tue, 24 Oct 2017 23:46:50 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r22sm513129ljr.16.2017.10.24.23.46.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 23:46:50 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com Date: Wed, 25 Oct 2017 08:45:28 +0200 Message-Id: <1508913930-30886-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508913930-30886-1-git-send-email-mw@semihalf.com> References: <1508913930-30886-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v2 6/8] Marvell/Armada: Enable dynamic DRAM size detection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Oct 2017 06:43:08 -0000 Instead of using hardcoded value in PcdSystemMemorySize PCD, obtain DRAM size directly from SoC registers, which are filled by firmware during early initialization stage. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 62 +++++++++++++++++++- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h | 25 ++++++++ 2 files changed, 86 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c index 978e4d3..bf0ebcf 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c @@ -50,6 +50,60 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS]; +// Obtain DRAM size basing on register values filled by early firmware. +STATIC +UINT64 +GetDramSize ( + IN OUT UINT64 *MemSize + ) +{ + UINT64 BaseAddr; + UINT8 RegionCode; + UINT8 Cs; + + *MemSize = 0; + + for (Cs = 0; Cs < DRAM_MAX_CS_NUM; Cs++) { + + /* Exit loop on first disabled DRAM CS */ + if (!DRAM_CS_ENABLED (Cs)) { + break; + } + + /* + * Sanity check for base address of next DRAM block. + * Only continuous space will be used. + */ + BaseAddr = GET_DRAM_REGION_BASE (Cs); + if (BaseAddr != *MemSize) { + DEBUG ((DEBUG_ERROR, + "%a: DRAM blocks are not contiguous, limit size to 0x%llx\n", + __FUNCTION__, + *MemSize)); + return EFI_SUCCESS; + } + + /* Decode area length for current CS from register value */ + RegionCode = GET_DRAM_REGION_SIZE_CODE (Cs); + if (DRAM_REGION_SIZE_CODE_INVALID (RegionCode)) { + DEBUG ((DEBUG_ERROR, + "%a: Invalid memory region code (0x%x) for CS#%d\n", + __FUNCTION__, + RegionCode, + Cs)); + return EFI_INVALID_PARAMETER; + } + + if (RegionCode <= 0x4) { + *MemSize += GET_DRAM_REGION_SIZE_ODD (RegionCode); + } else { + *MemSize += GET_DRAM_REGION_SIZE_EVEN (RegionCode); + } + } + + return EFI_SUCCESS; +} + /** Return the Virtual Memory Map of your platform @@ -72,12 +126,18 @@ ArmPlatformGetVirtualMemoryMap ( UINT64 MemHighSize; UINT64 ConfigSpaceBaseAddr; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + EFI_STATUS Status; ASSERT (VirtualMemoryMap != NULL); ConfigSpaceBaseAddr = FixedPcdGet64 (PcdConfigSpaceBaseAddress); - MemSize = FixedPcdGet64 (PcdSystemMemorySize); + // Obtain total memory size from the hardware. + Status = GetDramSize (&MemSize); + if (EFI_ERROR (Status)) { + MemSize = FixedPcdGet64 (PcdSystemMemorySize); + DEBUG ((DEBUG_ERROR, "Limit total memory size to %d MB\n", MemSize / 1024 / 1024)); + } if (DRAM_REMAP_ENABLED) { MemLowSize = MIN (DRAM_REMAP_TARGET, MemSize); diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h index 8101cf3..dd218d9 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h @@ -46,3 +46,28 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. (MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB #define DRAM_REMAP_TARGET \ (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS) + +#define DRAM_CH0_MMAP_LOW_REG(cs) (0xf0020200 + (cs) * 0x8) +#define DRAM_CS_VALID_ENABLED_MASK 0x1 +#define DRAM_AREA_LENGTH_OFFS 16 +#define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS) +#define DRAM_START_ADDRESS_L_OFFS 23 +#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFFS) +#define DRAM_CH0_MMAP_HIGH_REG(cs) (0xf0020204 + (cs) * 0x8) +#define DRAM_START_ADDR_HTOL_OFFS 32 + +#define DRAM_MAX_CS_NUM 8 + +#define DRAM_CS_ENABLED(Cs) \ + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_CS_VALID_ENABLED_MASK) +#define GET_DRAM_REGION_BASE(Cs) \ + ((UINT64)MmioRead32 (DRAM_CH0_MMAP_HIGH_REG ((Cs))) << \ + DRAM_START_ADDR_HTOL_OFFS) | \ + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_START_ADDRESS_L_MASK); +#define GET_DRAM_REGION_SIZE_CODE(Cs) \ + (MmioRead32 (DRAM_CH0_MMAP_LOW_REG ((Cs))) & \ + DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS +#define DRAM_REGION_SIZE_CODE_INVALID(C) \ + (((C) > 0x4 && (C) < 0x7) || (C) > 0x1b) +#define GET_DRAM_REGION_SIZE_ODD(C) ((UINT64)0x18000000 << (C)) +#define GET_DRAM_REGION_SIZE_EVEN(C) ((UINT64)1 << ((C) + 16)) -- 2.7.4