From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CDA9A2034C0A5 for ; Wed, 25 Oct 2017 08:15:13 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id l23so366331lfk.10 for ; Wed, 25 Oct 2017 08:18:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u/4LBy91XdKz2Xwr/MXOnH9qI99cX+U8zInXygOHD4M=; b=rqxkwd8f0c2hqfloyOV1N+axSPzqX9PNCjuFbAOKg4jNmbSLZvWF3qbej/+o6Lb8xH P7C88csoOadfYhqvHouEIUCzO5Nju1Ul1itL4XY5ibsixqVmo8hQ6jP1Rb1gsBcBC7bT mPDwT18kFJAcsmlGu6zRuLHK8TCcqf0cV8GqMS6c1mta9SEkkex9e4OXC1rMAfp8m6uj yYjL4sGmCfptFfIhl+FVICHl0ZDAzRkz1kcyVBQtSq0RY1802UwV5TbXTprwPjSTvc9g QDRdkWy8OCUmXLoIEDD2avWgKoqycjMtlabjbxb+SoJdTnMNE9yxWjQwM4B0zOmhT8wR o0ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u/4LBy91XdKz2Xwr/MXOnH9qI99cX+U8zInXygOHD4M=; b=n/dzd18BraW9NwYhDD6XS+T+NSwjp7P8mOd6p2XYnWdvzmAX/IY8zxmjjg5Zllbetd 8c19RaXManp1JLBjo10tK0bQk0FYXQo3iSc+N2KdtMoCmrmBY/qEQzRB3/LeRaMveRax UU1kJNtNS7Lmc0TEuMmZgnvBtKIce6OOc3sgkIXOBB8rFPCH1YE8rYqdwk/SVz4UMGLq q4ZEIF4J5dZQ0lau6ngqj5fvIuIhNR/Leid5k5fwX/TXFnAbZTFY9ZKTTvjbl+kfA8VL 9Ugxi8t2X34HE3ncePI/SduJycHocN9sqrzjRPMK+X8T3xYMVeL/Awdq76tYFVgTINXw kToQ== X-Gm-Message-State: AMCzsaVs2SjOTQACHreHNjiE79Pccw/ONWKi3MyrO9HHXavVBqviWv8M UKdd14jbXokxmlcpp0vvhDip5Ofk7mo= X-Google-Smtp-Source: ABhQp+Tt2pP75n933GjJAtoERuNYVtNxD5w179vDjhvbKKG5Q0HCyBbWtTMncC6ajc/G2pXi26Z7xQ== X-Received: by 10.46.84.1 with SMTP id i1mr8025582ljb.60.1508944737040; Wed, 25 Oct 2017 08:18:57 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id i62sm746461lji.42.2017.10.25.08.18.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Oct 2017 08:18:56 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, jinghua@marvell.com, mw@semihalf.com, jsd@semihalf.com Date: Wed, 25 Oct 2017 17:18:12 +0200 Message-Id: <1508944693-16315-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508944693-16315-1-git-send-email-mw@semihalf.com> References: <1508944693-16315-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v3 4/8] Marvell/Armada: Add support for DRAM remapping X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Oct 2017 15:15:14 -0000 The Armada 70x0/80x0 DRAM controller allows a single window of DRAM to be remapped to another location in the physical address space. Since DRAM starts at address 0, and normally exceeds 4GB on these systems, this allows us to free up some memory in the 32-bit addressable region for peripheral MMIO and PCI MMIO32 and CONFIG spaces. This patch adjusts memory blocks to the configuration done in ARM-TF. The remap parameters are otained directly from the registers. Moreover, the configuration space base address is now configurable via PCD, so that to satisfy a case, when remap is not enabled in the early firmware and ensure, that PcdSystemMemorySize is not overlapping it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Signed-off-by: Ard Biesheuvel --- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 2 + Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 90 +++++++++++++++----- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h | 48 +++++++++++ Platform/Marvell/Marvell.dec | 3 + 4 files changed, 124 insertions(+), 19 deletions(-) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf index 2e198c3..2236d9f 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -67,5 +67,7 @@ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress + [Ppis] gArmMpCoreInfoPpiGuid diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c index 74c9956..978e4d3 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c @@ -35,8 +35,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include #include #include +#include +#include #include +#include "Armada70x0LibMem.h" + // The total number of descriptors, including the final "end-of-table" descriptor. #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16 @@ -44,6 +48,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED +STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS]; + /** Return the Virtual Memory Map of your platform @@ -59,35 +65,81 @@ ArmPlatformGetVirtualMemoryMap ( IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap ) { - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; UINTN Index = 0; + UINT64 MemSize; + UINT64 MemLowSize; + UINT64 MemHighStart; + UINT64 MemHighSize; + UINT64 ConfigSpaceBaseAddr; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; ASSERT (VirtualMemoryMap != NULL); - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); - if (VirtualMemoryTable == NULL) { - return; + ConfigSpaceBaseAddr = FixedPcdGet64 (PcdConfigSpaceBaseAddress); + + MemSize = FixedPcdGet64 (PcdSystemMemorySize); + + if (DRAM_REMAP_ENABLED) { + MemLowSize = MIN (DRAM_REMAP_TARGET, MemSize); + MemHighStart = (UINT64)DRAM_REMAP_TARGET + DRAM_REMAP_SIZE; + MemHighSize = MemSize - MemLowSize; + } else { + MemLowSize = MIN (ConfigSpaceBaseAddr, MemSize); } - // DDR - VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); - VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); - VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); - VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; + ResourceAttributes = ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED + ); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdSystemMemoryBase), + MemLowSize + ); - // Configuration space 0xF000_0000 - 0xFFFF_FFFF - VirtualMemoryTable[++Index].PhysicalBase = 0xF0000000; - VirtualMemoryTable[Index].VirtualBase = 0xF0000000; - VirtualMemoryTable[Index].Length = 0x10000000; - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + // DDR + mVirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdSystemMemoryBase); + mVirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSystemMemoryBase); + mVirtualMemoryTable[Index].Length = MemLowSize; + mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; + + // Configuration space + mVirtualMemoryTable[++Index].PhysicalBase = ConfigSpaceBaseAddr; + mVirtualMemoryTable[Index].VirtualBase = ConfigSpaceBaseAddr; + mVirtualMemoryTable[Index].Length = SIZE_4GB - ConfigSpaceBaseAddr; + mVirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + if (MemSize > MemLowSize) { + // + // If we have more than MemLowSize worth of DRAM, the remainder will be + // mapped at the top of the remapped window. + // + mVirtualMemoryTable[++Index].PhysicalBase = MemHighStart; + mVirtualMemoryTable[Index].VirtualBase = MemHighStart; + mVirtualMemoryTable[Index].Length = MemHighSize; + mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + MemHighStart, + MemHighSize + ); + } // End of Table - VirtualMemoryTable[++Index].PhysicalBase = 0; - VirtualMemoryTable[Index].VirtualBase = 0; - VirtualMemoryTable[Index].Length = 0; - VirtualMemoryTable[Index].Attributes = 0; + mVirtualMemoryTable[++Index].PhysicalBase = 0; + mVirtualMemoryTable[Index].VirtualBase = 0; + mVirtualMemoryTable[Index].Length = 0; + mVirtualMemoryTable[Index].Attributes = 0; ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); - *VirtualMemoryMap = VirtualMemoryTable; + *VirtualMemoryMap = mVirtualMemoryTable; } diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h new file mode 100644 index 0000000..8101cf3 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h @@ -0,0 +1,48 @@ +/******************************************************************************* +Copyright (C) 2017 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define CCU_MC_RCR_REG 0xf0001700 +#define REMAP_EN_MASK 0x1 +#define REMAP_SIZE_OFFS 20 +#define REMAP_SIZE_MASK (0xfff << REMAP_SIZE_OFFS) +#define CCU_MC_RTBR_REG 0xf0001708 +#define TARGET_BASE_OFFS 10 +#define TARGET_BASE_MASK (0xfffff << TARGET_BASE_OFFS) + +#define DRAM_REMAP_ENABLED \ + (MmioRead32 (CCU_MC_RCR_REG) & REMAP_EN_MASK) +#define DRAM_REMAP_SIZE \ + (MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB +#define DRAM_REMAP_TARGET \ + (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS) diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 434d6cb..36a9d59 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -194,6 +194,9 @@ #TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 +#Configuration space + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT64|0x50000054 + [Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} -- 2.7.4